B.S. in Electrical Engineering or related field with 6+ years of IC package layout experience.
Proficient in Cadence Allegro Package Designer (APD).
Strong grasp of high-speed interconnects and package-level signal integrity.
Experience with substrate stack-up and routing constraints.
Excellent problem-solving skills and ability to work with global teams.
Responsibilities
Manage package substrate layout design for various advanced architectures.
Translate design specifications into layout constraints for internal and external resources.
Conduct design review meetings and communicate progress to stakeholders.
Collaborate on signal integrity and collect simulation results for package sign-off.
Perform design checks to ensure quality and manufacturability.
Work with OSATs and foundries to optimize design-for-manufacturability.
Maintain design libraries and documentation.
Benefits
On-site work environment in San Jose, CA.
Opportunity to work on cutting-edge packaging technologies.
Collaboration with a global team of experts.
Engagement in complex projects from prototype to high-volume manufacturing.
Full Job Description
Staff Engineer, Package Design
Location: San Jose, CA (on-site)
We are seeking a talented Senior Package Design Engineer to join our Platform Engineering team. This engineer will develop advanced package layouts for electro-optical ICs across flip-chip, 2.5D/3D, and heterogeneous integration packages, ensuring high performance, manufacturability, and reliability.
Essential Functions
Manage package substrate layout design for flip-chip, 2.5D/3D, and heterogeneous integration packages, including interposer and chiplet-based architectures.
Translate package design specifications into layout constraints and design rules for internal and external contract layout resources.
Run design review meetings for substrate layout, and communicate regular design progress, risks, and schedule status to engineering and program management.
Collaborate with internal stakeholders on signal integrity, power integrity, mechanical, thermal and physical design and collect simulation results for package sign off.
Perform DRC, LVS, and ERC checks to ensure design quality and manufacturability.
Collaborate with OSATs, foundries, and EDA vendors to drive design-for-manufacturability (DFM) and yield optimization.
Maintain package design libraries, flows, and documentation.
Basic Qualifications
B.S. in Electrical Engineering or related field plus 6+ years of experience in IC package layout and substrate design.
Proficiency with Cadence Allegro Package Designer (APD).
Solid understanding of high-speed interconnects (SerDes, Die-to-Die Interfaces), power delivery, and package-level signal integrity.
Experience with substrate stack-up definition, routing constraints, and package reliability requirements.
Strong problem-solving skills and ability to collaborate with a cross-functional, worldwide team across multiple time zones, including co-design with external vendor designers.
Preferred Qualifications
M.S. in Electrical Engineering or related field plus 6+ years of experience in IC package layout and substrate design.
Experience in heterogeneous integration, chiplet architectures, or silicon photonics packaging.
Knowledge of thermal and mechanical reliability considerations in advanced packaging, including warpage analysis.
Experience collaborating with OSATs and foundries on complex package substrates, from prototype through high-volume manufacturing (HVM).
Experience with Cadence SKILL or similar design-automation scripting to streamline layout and constraint generation.
Experience using agentic design and verification workflows (e.g., AI-assisted simulation setup, layout checking, or documentation generation).
Salary Range: $160,000 - $186,000
NOTE TO RECRUITERS: Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don't send candidates to Ayar Labs, and do not contact our managers.
