ResponsibilitiesMaxLinear is seeking a Senior Principal Digital SoC Design Engineer to join our Analog Mixed Signal (AMS) group in San Jose, CA. The AMS team develops a broad portfolio of integrated solutions spanning high speed and embedded connectivity interfaces (bridges, serial transceivers, isolators) and power management, supporting data center, industrial, and embedded platforms. In this role, you will lead digital architecture and RTL for a roadmap of products ranging from USB-based connectivity bridges to PCIe-to-USB host bridge devices, to complex embedded-processor SoCs for data center platform management, and will focus on the following:
- Lead digital architecture and RTL for USB device-side connectivity bridges, including multi-port serial (UART), I6C/SPI/GPIO bridging, endpoint/FIFO architecture, flow control, and OTP-based configurability and customization
- Architect and integrate PCIe-to-USB host bridge solutions, including PCIe endpoint and USB host controller (xHCI) integration, DMA engines, buffer management, interrupt and power-state handling, and driver-visible register architecture
- Define and lead digital architecture for complex embedded-processor SoCs for data center platform management, including multi-core Arm subsystems, memory controllers, high speed host interfaces, sideband management buses, and peripheral-rich I/O
- Drive platform security and management features, including secure boot, hardware root of trust, cryptographic checksum generator and checker, and host-to-management communication paths
- Maximize reuse of existing digital IP across product generations, and drive make, reuse, or license decisions for USB, PCIe, and other interface controllers and PHYs
- Define on-chip interconnect, clock/reset, low-power, and DFT architecture, and own RTL quality through lint, CDC/RDC, synthesis, timing constraints, and implementation closure
- Set verification strategy with the DV team, including compliance and interoperability readiness, emulation/FPGA prototyping, and firmware/driver co-verification
- Partner closely with analog/mixed-signal, PHY, firmware, software, package, test, and applications teams from concept through silicon bring up, compliance, qualification, and production
- Mentor senior engineers, lead design reviews, and act as the digital technical authority across connectivity and SoC roadmap
Qualifications- Deep hands-on expertise in SystemVerilog/Verilog RTL design, SoC micro-architecture, and complex top-level integration
- Strong working knowledge of USB 2.0/3.x device and host architectures (including xHCI) and PCIe endpoint architecture, with experience integrating licensed controller and PHY IP
- Experience with serial and peripheral interfaces (UART, I6C/I3C, SPI, GPIO) and bridge-type data paths, FIFOs, and DMA
- Experience integrating embedded Arm processor subsystems, DDR/memory controllers, bus fabrics (AMBA AXI/AHB/APB), and security IP; familiarity with data center server management concepts (e.g., eSPI, I3C, MCTP, hardware root of trust) is a strong plus
- Strong understanding of clock/reset, CDC/RDC, low-power design, timing constraints, synthesis, DFT, and physical design trade-offs
- Track record delivering multiple SoCs from architecture through tapeout, silicon bring up, compliance certification, and high-volume production
- Experience working with external design partners and IP vendors, and ability to lead technically across multiple disciplines and global teams
- BS in Electrical Engineering or related + 15 years of experience, or MS + 12 years of experience, or Ph.D. + 9 years of experience
Compensation and BenefitsMaxLinear has a Total Compensation philosophy which includes base salary and annual discretionary bonus eligibility and many positions also include stock-based compensation.
MaxLinear's good faith estimate starting base salary range is: $200,000 to $250,000 Annually
We offer competitive benefits designed to support employee health, welfare, and retirement and some highlights are: health care benefits, 401k savings plan, Employee Stock Purchase Plan (ESPP), and paid time off.
The actual starting base salary will be determined by the match to certain role-related criteria such as educational degree(s) or equivalent, relevant work experience, skillset needed for the role, and geographic location; this is not an all-inclusive list as some roles may require unique skills or experience.
