OverviewWe are looking for a PDN expert to accelerate development of advanced power distribution solutions for next-generation 2.5D and 3DIC products. This role is strategically critical as customer demand for higher performance continues to rise and power density trends exceed 4 W/mm². The engineer will identify bottlenecks in current offerings, define next-generation design flows, and partner with R&D, packaging, and EDA vendors to deliver robust solutions that support TSMC's HPC roadmap.
This position requires both hands-on technical expertise and cross-functional leadership to bring new design methodologies from concept to reference flow, enabling customer success.
Responsibilities:- Review and analyze current PDN reference flows and test vehicles; identify weaknesses and propose design improvements.
- Develop and validate PDN topologies and voltage regulator integration strategies for advanced 3DIC/HPC products.
- Collaborate with R&D, advanced packaging, and decoupling capacitance teams to ensure new solutions are manufacturable and scalable.
- Work closely with EDA vendors (Cadence, Synopsys, Ansys) to enable and certify PDN design and analysis flows.
- Provide end-to-end ownership of PDN design flow development and reference methodologies for internal and external customers.
- Mentor junior engineers on PDN concepts and high-power design practices.
Required Skills:- Master's/PhD in Electrical Engineering with at least 15 years of working experience with specialization in power distribution networks, voltage regulators, or electromagnetics.
- Proven experience designing PDNs for high-power systems (≥42 W/mm²).
- Familiarity with best PDN payout theory and practices, voltage regulator design, in-package integration, and decoupling capacitor technologies, and usage.
- Proficiency with EDA tools and interfacing languages (Tcl, Python): Cadence: Allegro, Virtuoso, Sigrity, Voltus; Ansys: HFSS, RedHawk.
- Strong problem-solving ability with capacity to investigate bottlenecks and propose actionable solutions.
- Strong written and verbal communication skills; ability to work across technical and business teams.
Preferred Skills:- Research or patents in PDN layout, voltage regulators, inductor technologies, or decoupling capacitance improvements.
- Experience with EDA flow development or building analysis tools.
- Programming skills (C/C++, Python, TCL, SKILL, Perl) for automation and data exchange.
- Knowledge of distributed voltage regulator coordination techniques (aka ganging) for large PDN designs.
LocationPrimary location: San Jose, CA or Hsin Chu, Taiwan.
Relocation support and visa sponsorship may be considered for exceptional candidates.
Pay Transparency / Benefits statementAt TSMC, your base pay is only part of your overall total compensation package. At the time of this posting, this role typically pays a base salary between $153,500 and $250,000 per year . The range displayed reflects the minimum and maximum target for new hires. Actual pay may be more or less than the posted range. Factors that influence pay include the individual's skills, qualifications, education, experience and the position level and location. TSMC's total compensation package consists of market competitive pay, allowances, bonuses, and comprehensive benefits. We also offer extensive development opportunities and programs.
For roles hired outside of California, including other U.S. states or international locations such as Taiwan, compensation may vary in accordance with local market practices, legal requirements, and TSMC's regional compensation framework.
Date: Sep 19, 2026
Country/Region: US
City: San Jose
Company: TSMC Technology, Inc.
