Job Description
We are seeking an experienced engineer to join our team researching advanced defect modeling, testing, screening, and analysis for next-generation semiconductor processes and 3D packaging technologies. This role is strategically critical for TSMC: it represents a multi-year journey to pioneer new approaches to defect modeling in advanced packaging. Defect modeling in this space is still an emerging discipline, with global leaders actively defining the standards. This position provides a unique opportunity to keep TSMC at the forefront of innovation and shape the methodologies that will guide the industry.
The successful candidate will develop methodologies and tools to model and simulate defects, assess their impact on performance, optimize testing strategies, and innovate beyond the limitations of current testing instruments. This engineer will collaborate across design, process, test, and reliability functions to ensure the functionality and yield of advanced 2.5D/3D packaging technologies.
Key Responsibilities
• Defect Modeling & Analysis: Develop defect models for 2D structures (standard cells, FEOL/MEOL/BEOL layers) and 3D structures such as TSVs, interconnects, hybrid bonding, and chip stacking. Perform root-cause analyses of electrical, mechanical, and thermal defects in advanced packages and address them using design-for-test methods.
• Simulation & ATPG: Conduct SPICE simulations to evaluate circuit behavior under defect conditions and identify failure scenarios. Use EDA ATPG tools (or develop internal methods) to generate defect-oriented test patterns. A strong understanding of standard cell layout, parasitic extraction, and simulation is required.
• Testing & Probing Structures: Assess the influence of probing techniques and test structure designs on defect detection and reliability learning. Develop and implement methodologies leveraging test/probe structures to monitor process variations and enhance yield. Collaborate closely with internal partners (DPT Standard Cell, PE/Fab, QR) and external partners (EDA vendors).
• Research & Optimization: Implement advanced test methodologies for defect detection at both chip and package levels. Stay updated on evolving technologies and defect mechanisms in semiconductor manufacturing. Contribute to patents and publications in leading conferences and journals.
• Cross-Functional Collaboration: Approximately 75% of this role will focus on fundamental research, with ~30% involving collaboration across design, process, and manufacturing teams. The role demands a proactive mindset and flexibility to push solutions forward across geographies and stakeholders.
Required Qualifications
• Education: Master's or Ph.D. in Computer Engineering, Semiconductor Physics, or a related field.
• Experience: At least 15+ years of expertise in failure mechanisms, defect physics, testing, or reliability analysis for semiconductor devices, including 2D and 3D structures.
• Technical Skills: Proficiency with SPICE simulation tools (HSPICE, PSPICE, Spectre), LVS/DRC verification tools, and DFT/ATPG methodologies for packaging and advanced nodes. Programming or scripting skills (Python, Perl, C++) for automation and data analysis are required; experience with AI/ML for defect prediction is a plus.
• Domain Knowledge: Deep understanding of defect physics, testing/probing structures, and their impact on defect detection, characterization, and yield learning in advanced process nodes and 3D packaging. Familiarity with thermal and mechanical considerations in 3D integration.
• Industry Exposure: Demonstrated contributions through patents, publications, or conference presentations in defect modeling, reliability, or advanced packaging.
Location
San Jose, CA. Visa sponsorship may be considered for exceptional candidates.
Why This Role?
This is a career-defining opportunity to shape the methodologies and tools that will underpin the next decade of semiconductor innovation. Success requires not only technical expertise but also the ability to bring forward new ideas, and collaborate across diverse teams in San Jose, Taiwan, and Japan.
Date: Jul 16, 2026
Country/Region: US
City: San Jose
Company: TSMC Technology, Inc.
