Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
10 years of experience in Physical Design implementation and PPA optimization.
Expertise in high-performance, low-power physical design and design convergence techniques.
Master's degree or PhD in a relevant field is preferred.
Experience with CPU class physical design methodologies and AI/ML-assisted optimization flows.
Proven ability to lead cross-functional engineering initiatives.
Understanding of power grid design and low-power implementation techniques.
Responsibilities
Lead physical design strategy and execution for critical CPU blocks.
Pioneer new methodologies and AI/ML techniques to enhance PPA.
Resolve complex timing and power grid issues in iterative processes.
Drive technical roadmaps and mentor senior engineers.
Influence architectural decisions across cross-functional teams.
Benefits
Flexible working locations in Mountain View, CA or Austin, TX.
Opportunities for professional development and mentorship.
Access to cutting-edge technology and tools.
Collaborative work environment with cross-functional teams.
Full Job Description
info_outline X Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Mountain View, CA, USA; Austin, TX, USA.
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
10 years of experience in Physical Design implementation, PPA optimization and design signoff convergence activities.
Experience in high-performance, low-power physical design implementation or design convergence techniques with custom or industry standard synthesis, PnR and signoff tools.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Experience with CPU class physical design methodologies, custom tool enhancements, or AI/ML-assisted PPA optimization flows.
Experience leading cross-functional engineering initiatives across Architecture, RTL, DFT, and Technology partners to optimize sub-system microarchitecture.
Understanding of power grid design, EMIR constraints, and low-power implementation techniques.
Responsibilities
Lead end-to-end physical design strategy and execution for top-level and critical CPU blocks across advanced process nodes.
Pioneer novel Physical Design methodologies, tool flows, and AI/ML optimization techniques to maximize PPA (Power, Performance, Area).
Resolve complex timing, power grid, EMIR, and physical verification bottlenecks in tight iteration loops.
Drive technical roadmaps, mentor senior engineering peers, and influence architectural trade-offs across cross-functional teams.
About Google
Google is a multinational technology company that specializes in Internet-related services and products. These include online advertising technologies, search engine, cloud computing, software, and hardware. Google was founded in 1998 by Larry Page and Sergey Brin while they were Ph.D. students at Stanford University. The company has grown tremendously since then and has become one of the most valuable companies in the world. Google's mission is to organize the world's information and make it universally accessible and useful.
