10+ years of ASIC physical design experience, tailored to degree level.
Extensive tapeout experience in cutting-edge technology nodes (7nm, 5nm, 3nm).
Advanced proficiency with EDA tools from Cadence, including Innovus and Tempus.
Strong understanding of physically aware synthesis and power domain analysis.
Expertise in Electromigration/IR-drop (EM/IR) cleanup.
Responsibilities
Own physical implementation of SoCs or complex digital blocks from RTL to GDSII.
Manage floor-planning, bump planning, power grid design, and clock tree synthesis for optimization.
Resolve timing, congestion, and EM/IR issues in collaboration with Frontend Designers.
Conduct Static Timing Analysis (STA) and physical verification, addressing DRC and LVS violations.
Drive automation and enhance flow robustness through scripting in Tcl, Python, or Perl.
Collaborate with architects, logic designers, and analog teams to ensure tapeout readiness.
Benefits
Opportunity to work on cutting-edge technology in advanced nodes.
Collaborative environment with cross-functional teams.
Focus on innovation through methodology development and automation.
Access to industry-standard EDA tools and resources.
Full Job Description
Principal Physical Design Engineer
Core Responsibilities • RTL-to-GDSII Execution: Own physical implementation of System-on-Chips (SoCs) or complex digital blocks. • Design Optimization: Manage floor-planning, bump planning, power grid design, and clock tree synthesis (CTS) to optimize chip performance. • Design Convergence: Resolve timing, congestions, EM/IR issues together with Frontend Designers • Signoff & Verification: Run Static Timing Analysis (STA) and physical verification. Fix Design Rule Checking (DRC) and Layout Versus Schematic (LVS) violations. • Methodology Development: Drive automation and improve flow robustness using scripting languages like Tcl, Python, or Perl. • Cross-Functional Leadership: Partner with architects, logic designers, and analog design team for tapeout readiness.
Key Qualifications • Experience: 10+ years of relevant ASIC physical design experience (depending on degree level). • Process Knowledge: Deep tapeout experience in advanced technology nodes (e.g., 7nm, 5nm, 3nm). • Tool Mastery: Advanced proficiency with industry-standard EDA tools from vendors like Cadence (e.g., Innovus, , Tempus, Voltus, Pegasus, Calibre). • Technical Concepts: Expertise in physically aware synthesis, power domain analysis, and Electromigration/IR-drop (EM/IR) cleanup.
