Application close date:
Applications will be accepted on an ongoing basis until the requisition is closed.
As a Principal Modem SOC Design Engineer on the ASIC Engineering SOC Team, you will be a technical design leader for the TeraWave satellite communication System on Chip (SOC). This individual contributor role carries technical leadership scope. You will lead RTL design for the modem SOC and its subsystems, define microarchitecture from communication system specifications, and drive integration across the modem PHY, Arm compute, debug, and IO infrastructure. As the technical interface among the system architecture, SOC architecture, software architecture, performance modeling, and FPGA prototyping teams, you will align design decisions from specification through production silicon.
Responsibilities- Lead RTL design in Verilog or System Verilog for the modem SOC and its subsystems
- Define microarchitecture based on satellite communication system specifications and performance requirements
- Develop Arm compute subsystem logic, including AXI interconnect and SRAM controller integration
- Integrate debug subsystem components using Arm CoreSight architecture and associated trace infrastructure
- Drive subsystem and SOC-level integration, including clock, reset, and general-purpose IO (GPIO) subsystems
- Serve as the technical interface to the system architecture, SOC architecture, and software architecture teams
- Collaborate with performance modeling and FPGA prototyping teams on design decisions and validation
Minimum Qualifications- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field
- 12+ years of experience in digital ASIC or SOC RTL design
- Experience defining microarchitecture for modem or communication SOC blocks from system specifications
- Experience with Arm compute subsystem design, including AXI interconnect and SRAM controllers
- Experience with LPDDR4, LPDDR5, LPDDR6, or other high-speed memory interface subsystems
- Experience with high-speed Gigabit Ethernet interface subsystems
- Experience with SOC-level integration, including bus fabric, clock, and reset architecture
- Experience with debug subsystem design using Arm CoreSight components
- Experience with synthesis, timing constraint development, and timing closure support
Preferred Qualifications- Master's degree in Electrical Engineering, Computer Engineering, or a related technical field
- Experience with RTL design in Verilog or System Verilog for modem datapath or PHY IP blocks
- Experience with signal processing hardware such as filters, FFTs, equalizers, or forward error correction (FEC)
Base Pay Range for:
CA applicants is $269,175.00 - $376,843.95WA applicants is $269,175.00 - $376,843.95
Other site ranges may differCulture StatementDon't meet all desired requirements? Studies have shown that some people are less likely to apply to jobs unless they meet every single desired qualification. At Blue Origin, we are dedicated to building an authentic workplace, so if you're excited about this role but your past experience doesn't align perfectly with every desired qualification in the job description, we encourage you to apply anyway. You may be just the right candidate for this or other roles.
Benefits- Benefits include: Medical, dental, vision, basic and supplemental life insurance, paid parental leave, short and long-term disability, 401(k) with a company match of up to 5%, and an Education Support Program.
- Stock Options for all regular employees (working at least 20 hours/week)
- Paid Time Off: Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays.
- Dependent on role type and job level, employees may be eligible for benefits and bonuses based on the company's intent to reward individual contributions and enable them to share in the company's results, or other factors at the company's sole discretion. Bonus amounts and eligibility are not guaranteed and subject to change and cancellation. Please check with your recruiter for more details.
