BS in Electrical Engineering, Physics, or a related field.
5+ years (Sr. Engineer) or 8+ years (Staff Engineer) in high-speed link modeling or DSP for wireline communication.
Strong knowledge of analog front-end blocks and DSP for high-speed links.
Proficiency in Verilog-A and mixed-signal simulation methodologies.
Experience with statistical circuit analysis methods like corners and Monte Carlo.
Strong Python skills for scientific computing and data analysis.
Responsibilities
Build and maintain compact models for analog front end and DSP chain.
Co-design Verilog-A models for electrical/optical interfaces with AMS designers.
Anchor models to silicon by reconciling simulation with measurement.
Feed accurate electrical models into link studies, collaborating on specs and yield.
Collaborate across teams to ensure modeling aligns with product roadmap.
Run end-to-end link simulations to evaluate device and architecture choices.
Benefits
On-site work environment in San Jose, CA.
Opportunity to shape long-term technology roadmaps.
Engagement in next-generation link architecture exploration.
Full Job Description
Sr. Staff Engineer, Electrical Link Architecture
Location: San Jose, CA (on-site)
Joining our Link Design and Architecture team, you will own the electrical-side modeling that drives our silicon photonics I/O platform - the analog front end, the DSP that closes the link, and the models that make circuits and photonics co-simulate end-to-end. This team is responsible for the robustness and performance of the optical links that power our technology, from component-level modeling through architecture definition, full link analysis, specification development, and yield prediction. Beyond today's products, the team drives the exploration of next-generation link architectures and directly shapes our long-term technology roadmaps.
Essential Functions
Build and maintain compact models of the analog front end and the DSP chain at the fidelity needed for accurate BER and link-margin prediction.
Co-design Verilog-A models of the electrical/optical interface - modulators, photodetectors, and the blocks where circuits and photonics meet - with analog / mixed-signal (AMS) designers.
Anchor models to silicon by working with validation engineers to reconcile simulation against measurement.
Feed accurate electrical models into link studies, partnering with statistical link modeling experts on specs and yield using standard circuit-design methods (corners, Monte Carlo).
Collaborate across AMS, photonics, and validation to keep the modeling stack coherent with the product roadmap.
Run end-to-end link simulations to evaluate device and architecture choices, informing current product design and future roadmap exploration.
Required Qualifications
BS in Electrical Engineering, Physics, or a related field.
5+ years (Sr. Engineer) or 8+ years (Staff Engineer) of experience in high-speed link modeling, SerDes architecture, analog/mixed-signal modeling, or DSP for wireline communication.
Strong working knowledge of analog front-end blocks and the DSP that closes high-speed links.
Proficiency in Verilog-A and mixed-signal simulation methodologies.
Experience with statistical circuit analysis methods (corners, Monte Carlo).
Strong Python skills for scientific computing and data analysis.
Preferred Qualifications
Prior industry experience architecting and deploying SerDes into a shipping product.
MS or Ph.D in Electrical Engineering, Physics, or a related field.
Hands-on experience with silicon bring-up, validation, or link characterization.
Working knowledge of analog circuit fundamentals and high-speed signal integrity concepts.
Familiarity with Cadence Virtuoso / ADE / Spectre.
Familiarity with optical transceiver principles, modulation formats, and industry standards.
Salary range: $197,000 - $270,000
NOTE TO RECRUITERS: Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don't send candidates to Ayar Labs, and do not contact our managers.
