DescriptionWe're looking for a Sr. Principal-level DFT leader to own that foundation. This isn't a role focused on executing someone else's test plan - you'll be the person defining how SiMa approaches Design for Test at the architecture level, then staying hands-on through execution, tape-out, and pattern bring-up across our next generation of SoCs.
What you'll doYou'll set the DFT architecture and methodology strategy for SiMa's upcoming industrial, robotic, and automotive ICs - decisions that ripple through every downstream team touching the chip. From there, you'll drive execution of that strategy directly, working shoulder-to-shoulder with RTL design, verification, and physical design teams to make sure the architecture you've defined actually holds up in silicon. You'll also be a technical anchor for the broader DFT team - not managing them on paper, but enabling their success day to day, unblocking hard problems, and raising the technical bar across the group.
This is a role for someone who wants ownership of the whole DFT lifecycle, not one slice of it - architecture through tape-out through pattern bring-up, on advanced finFET nodes, across multiple ICs.
Job Title: Sr. Principal DFT Engineer Job Location: San Jose, CA (This position requires a full-time, on-site presence in our San Jose, CA office) J
ob ID: AI2533 Key Responsibilities:- Technical leadership across various DFT endeavors at SiMa.
- DFT architecture and methodology development for latest industrial, robotic, and automotive ICs.
- Responsible for the execution of above DFT architecture/methodology in future SiMa SoC(s).
- Work closely with other members of DFT team to enable their success.
- Work across all H/W functions (RTL design, verification, and physical design) towards the successful implementation of above DFT strategies.
Required Background:- BSEE with 18+ years of experience or MSEE/PhD with 16+ years of experience
- Commanding knowledge of all aspects of DFT
- Experience with end-to-end DFT execution from architecture to tape-out to pattern bringup across multiple ICs in advanced finFET technology.
- In-depth knowledge of VLSI design as well as hardware description languages such as Verilog and System Verilog.
- Deep hands-on experience with latest EDA tools like Synopsys SMS/Testmax or Mentor Tessent.
- Good working knowledge of non-DFT EDA tools like VCS/Verdi, Fusion Compiler, PrimeTime, PrimePower, RedHawk, StarRC, etc. is preferred plus.
- Strong problem solving and debug capabilities is must.
- Should be proficient at working with cross functional and cross site teams.
- Must possess good communication skills, be a self-driven individual, and a good team player.
Personal attributes:Can-do attitude. Strong technical leadership attributes. Curious, creative, and good at solving problems. Execution and results oriented. Self-driven, Thinks Big and is highly accountable. Good communication skills.
The annual salary for this position ranges from $231,100 - $358,200. The actual annual salary offered will depend on several factors, including - among others - job-related skills, experience, technical expertise, qualifications, work location, and business needs. The annual salary range for this position is subject to change and may be adjusted in the future.
In addition to base salary, this role is also eligible for private company equity, and a comprehensive package of employee benefits. Please note that the salary ranges listed for U.S. roles reflect base salary only and do not include equity or other forms of compensation.
