Position: Senior Staff ASIC Design Engineer - AI/ML Hardware IPLocation: On-site in Canada
We're working with a global semiconductor leader to hire a
Senior Staff ASIC Design Engineer focused on developing cutting-edge AI/ML hardware IP. This role is designed for a senior contributor who can lead architecture definition, RTL development, and integration across complex SoC designs. You'll work cross-functionally to optimize performance, area, power, and verification coverage in highly scalable AI/ML systems.
Key Responsibilities:- Define and implement micro-architecture based on high-level AI/ML design requirements.
- Own RTL development (Verilog/SystemVerilog), optimizing for performance, area, and power.
- Integrate multiple sub-IP blocks into cohesive larger systems.
- Drive Linting, CDC, Synthesis, and Power Intent flow execution and analysis.
- Partner closely with verification teams on test plans, debug, and functional coverage.
- Develop SVA assertions to support formal and white-box verification strategies.
- Influence and lead cross-functional execution, promoting best practices in design and integration.
Ideal Experience & Skills:- 6+ years of ASIC design, RTL, and integration experience (or equivalent: Master's + 5, PhD + 4).
- Advanced RTL design skills, especially in Verilog/SystemVerilog.
- Demonstrated ownership of complex SoC blocks or subsystems.
- Strong background in:
- Clock/reset architecture, FIFOs, memory control
- Power-aware design and low-power optimization (UPF, CLP, PowerPro)
- Bus protocols (AHB, AXI)
- AI/ML-specific hardware acceleration blocks
- Deep toolchain knowledge:
- Simulation (VCS, Verdi, Questa, Xcelium)
- CDC/lint/formal tools (Spyglass, 0-in, Formality)
- Synthesis/timing (DCG/NXT, Primetime)
- Scripting experience (Python, Perl, TCL, C) to support design automation.
Education & Work Authorization:- Bachelor's, Master's, or PhD in Electrical Engineering or related field.
- Must be legally authorized to work on-site in Canada.
