Senior Digital Verification Engineer

Efficient Computer

$160K — $210K *
Information Technology
8 - 10 years of experience
Job Overview by Ladders

Qualifications

  • Bachelor's or Master's/PhD in Electrical Engineering, Computer Engineering, or related field.
  • 10+ years of experience in ASIC/SoC design verification with full cycle ownership.
  • Expertise in UVM-based testbench architecture and constrained-random verification methodology.
  • C/C++ experience for modeling or verification purposes.
  • Proven track record in driving functional and code coverage to tapeout sign-off.
  • Demonstrated debugging skills for complex simulation failures.
  • Proficiency in Python for automation and regression flow development.

Responsibilities

  • Drive functional verification of complex SoC/IP designs from specification through tapeout.
  • Influence products and processes in early product development stages.
  • Collaborate with the verification team to ensure robust testbench architecture.
  • Analyze verification risks and communicate status to peers and leadership.
  • Develop and implement automated tests and coverage analysis.
  • Debug simulation failures and stabilize the verification process.
  • Support the transition from development to market release and scaled production.

Benefits

  • Comprehensive benefits package.
  • Opportunities for meaningful equity in the company.
Full Job Description
We are looking for an experienced Design Verification Engineer to drive the functional verification of complex SoC/IP designs from specification through tapeout on a newly formed verification team. This is a great opportunity to have an influence on our products and processes as we move from the initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond!

Required Qualifications & Experience
  • Education: Bachelor's or Master's/PhD degree in Electrical Engineering, Computer Engineering, or a related field.
  • Experience: 10+ years of progressive experience in ASIC/SoC design verification with multiple full cycles of ownership from testbench architecture through tapeout.
  • UVM and SystemVerilog: Expertise in UVM-based testbench architecture and constrained-random verification methodology
  • C/C++ experience for modelling or verification.
  • Coverage Closure: Demonstrated track record of driving functional and code coverage to tapeout sign-off on complex, multi-million-gate SoC/ASIC designs.
  • Debug Skills: Proven ability to debug complex simulation failures.
  • Scripting & Automation: Proficiency in Python for test automation, log analysis, coverage post-processing, and regression flow development.
  • Communication: Ability to clearly communicate verification risk, status and tradeoffs to technical peers and program leadership.

Ways to stand out :
  • Experience in Formal verification (JasperGold or similar).
  • Experience building or using AI Agentic flows for DV.
  • Software/Firmware based testing experience and working with software teams pre-silicon
  • Post-silicon experience
  • SoC Architecture: Understanding and experience in some of the following areas : processors (ARM, RISC-V), interconnects (AMBA AXI/ACE/CHI), memory controllers, DMA engines, interrupt controllers, and standard peripherals.
  • Power aware verification and UPF

We offer a competitive salary for this role, generally ranging from $160,000 to $210,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.

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