Please Note:1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)2. If you already have a Candidate Account, please Sign-In before you apply.Job Description:Principal Physical Design Engineer - ASIC Products Division (APD)About the RoleBroadcom's ASIC Products Division (APD) is looking for a
Principal Physical Design Engineer to lead physical design implementation tasks for next-generation high-performance networking, AI/ML accelerators, and custom cloud ASICs. In this role, you will drive complex block-level floorplanning, synthesis, Place and Route (P&R), clock tree synthesis (CTS), timing closure, and signoff across cutting-edge deep sub-micron nodes (N5/N3/N2/A14).
Responsibilities- Lead block-level and top-level implementation from floorplanning to GDSII stream-out using Cadence Innovus
- Drive floorplanning, placement, CTS, routing, and timing/power optimization on advanced technology nodes (5nm, 3nm, 2nm) using multi-patterning and complex metal stacks.
- Perform multi-corner multi-mode (MCMM) static timing analysis (STA), signal integrity (SI) optimization, and power grid optimization (static/dynamic IR-drop, EM) for signoff using PrimeTime, Voltus, or RedHawk.
Qualifications & Requirements- B.S. or M.S. degree in Electrical Engineering, Computer Engineering, or a related technical field.
- 12+ years of hands-on physical design experience successfully taping out complex high-frequency, ultra-large-scale networking or AI ASICs.
- Direct experience executing tape outs in TSMC advanced nodes (N7, N5, N3) or equivalent foundry processes.
- High proficiency in major physical design tool flows:
- P&R: Cadence Innovus
- Timing/STA: Synopsys PrimeTime or Cadence Tempus
- Extraction & IR/EM: StarRC / QRC, RedHawk
- DRC/LVS: Siemens Calibre
- Deploy AI automation within the APD flows to improve efficiency, reduce runtime.
- Excellent technical leadership, problem-solving, and cross-functional communication skills.
Preferred Qualifications- Strong background in high-speed clock network implementation (H-tree, mesh, low-power CTS).
- Experience with power-aware implementation flows (UPF/CPF, multi-voltage domains, clock/power gating).
Compensation and BenefitsThe annual base salary range for this position is USD 143,800.00 To USD 230,000.00
As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence. 
