Principal FPGA Micro-Architect

Job Description:

We are seeking a Principal FPGA Micro-Architect with deep expertise in programmable logic fabric design and a track record of delivering next-generation FPGA devices from concept to silicon. You will define and drive the micro-architecture of Lattice's FPGA fabric primitives, optimizing for power, performance, area, and utilization across device families. You will shape the architecture of next-generation FPGAs targeting Physical AI, Robotics, Space, Data Centers, and edge applications - markets where Lattice's low-power leadership is a decisive advantage.

Key Responsibilities
• Define micro-architecture of core fabric primitives: Programmable Logic Elements, DSP blocks, embedded memory blocks, interconnect routing, configuration memory, carry chains, and clocking structures
• Drive fabric PPAU (power, performance, area, and utilization) optimization; evaluate implementation and routing feasibility and drive design trade-offs for modularity and scalability across device generations
• Develop SystemC/C++ architectural models to drive performance analysis and evaluate fabric design trade-offs ahead of RTL/schematic availability
• Lead advanced low-power fabric design including clock and power islands, power gating, dual-rail architectures, and dynamic power mode switching
• Drive software primitive definition and implementation strategy, ensuring fabric elements are optimally mapped to CAD tools and customer design flows for maximum usability
• Partner with architecture, DV, firmware, and CAD teams across the full product lifecycle from concept through silicon validation and post-silicon debug
• Apply agentic AI methodologies to scale and accelerate micro-architecture exploration and design execution

Required Qualifications
• MS/PhD in Electrical or Computer Engineering with 15+ years of FPGA fabric micro-architecture experience
• Established track record of delivering FPGA fabric primitives from architecture definition through tape-out and silicon validation, with demonstrated ability to define software primitives and drive implementation strategy for optimal fabric usability in customer design flows
• Deep expertise in FPGA fabric elements including logic elements, DSP blocks, embedded memory blocks, interconnect routing muxes, carry chains, and clocking structures
• Proficiency in SystemVerilog/Verilog and SystemC/C++ architectural modeling for performance analysis and design trade-off evaluation
• Deep experience in advanced low-power design: clock and power islands, power gating, multi-rail, and dynamic power mode switching
• Extensive hands-on experience in silicon validation and post-silicon debug of FPGA fabric blocks, including bring-up, characterization, and root-cause analysis of fabric-level sightings
• Strong written and oral communication skills with a history of executive-level presentations

Pay & Benefits

Consistent with Lattice Semiconductor values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location. Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience.

For candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location. The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.

Base Pay Range
250,000.00

In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity. In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more!