Principal / Senior Principal Engineer, Advanced PackagingLocation: San Jose, CA (on-site)
Ayar Labs is seeking a Principal or Senior Principal Advanced Packaging Engineer to help shape the Co-Packaged Optics revolution in High-Performance Computing.
The primary responsibility of the Advanced Packaging Engineer is to define an advanced packaging technology roadmap, enabling the transition from successful design of validation systems to incorporation into high-volume manufacturing. The Advanced Packaging Engineer is expected to drive the electrical package engineering team to success with first principles, collaboration and discipline.
Prior experience in photonics is not necessary; however, the candidate must display a propensity for growth. The exceptional candidate must be highly motivated and energetic, willing to collaborate with diverse, cross-functional teams. This is an on-site role in Ayar Labs' San Jose Headquarter office.
Essential Functions- Design and develop the package architecture from silicon validation to high-volume product adoption.
- Maintain technical documentation for delivery to vendors, manufacturing partners and customers.
- Provide mentorship to engineering staff throughout project execution.
- Collaborate with engineering and program management to make accurate risk assessments, driving critical project schedules.
- Coordinate with internal and external stakeholders including Reliability, Silicon Engineering, Validation, Design Service Vendors, substrate suppliers, and OSAT/assembly partners.
- Ensure appropriate standards for DFM, DFA, and DFR (design-for-manufacturability, -assembly, and -reliability) are met for all package deliverables.
- Define package-level specifications for high-speed electrical interfaces, including SerDes, PCIe, and die-to-die (D2D) interconnects.
- Define company standards for power distribution network (PDN) design, simulation and verification.
Basic Qualifications- Advanced degree in Electrical Engineering or related field plus 12+ years (15+ years for Senior Principal) of industry experience.
- Demonstrated experience in the design and validation of advanced package technology for SerDes, PCIe, die-to-die (D2D) interconnects, HPC .
- Expert in Power and Signal Integrity analysis and design, with proficiency in at least one major simulation tool (e.g., Ansys HFSS, SIwave, Cadence Clarity, PowerSI).
- Strong understanding of warpage, thermal and mechanical analysis of substrate technology.
- Exceptional technical communication skills.
Preferred Qualifications- Experience in the design of high-power advanced package designs (>1kW).
- Experience in optical transceiver design and validation, especially co-packaged optics.
- Experience using agentic design and verification workflows (e.g., AI-assisted simulation setup, layout checking, or documentation generation).
- Track record of new product introduction (NPI), from concept through development and production release.
- Familiarity with JEDEC and other industry reliability/qualification standards.
Salary Range: $224,000 - $261,000
NOTE TO RECRUITERS:
Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don't send candidates to Ayar Labs, and do not contact our managers.
