Principal Digital IC Design Engineer
Posting Start Date: 11/2/26
Job Location(s): TX,Campbell Rd
Requisition ID: 78933
Job Description:
DescriptionWe are seeking a experienced and visionary Principal ASIC Engineer to lead our next-generation silicon development. In this high-impact technical leadership role, you will own the full-flow ASIC development lifecycle, driving projects from initial architectural concepts and RTL design down to physical sign-off and silicon bring-up.
The ideal candidate possesses deep expertise across both front-end design and back-end implementation, serving as a strategic authority who bridges the gap between hardware architecture, microarchitecture, and complex physical layout constraints.
ResponsibilitiesTechnical Leadership & Strategy
- Define, establish, and optimize cutting-edge ASIC design methodologies and full-flow architectures across the organization.
- Act as the chief technical authority to align cross-functional domains including Architecture, RTL Design, Verification, and Physical Design.
- Provide expert guidance on complex engineering trade-offs evaluating Power, Performance, and Area (PPA).
Front-End Design & Architecture
- Translate complex system-level product requirements into functional SoC/ASIC microarchitectures.
- Write high-quality, scalable, and synthesizable hardware description code using SystemVerilog/Verilog.
- Collaborate closely with Design Verification (DV) teams to review test plans and implement advanced Design for Testability (DFT) structures
Back-End & Physical Implementation
- Drive full chip-level and block-level execution through synthesis, floorplanning, and automated Place & Route (P&R) flows.
- Formulate and sign off on rigorous Timing Constraints and execute deep Static Timing Analysis (STA) to resolve setup/hold violations.
- Oversee structural physical verification including DRC, LVS, and ERC checks to guarantee tape-out readiness.
Required Experience and SkillsEducation & Experience
- Bachelor's degree in Electrical Engineering
- 12+ years of expereince or equivalent amount of advanced education and experience in direct, practical industry experience in digital ASIC design and implementation with a proven history of multiple successful commercial tape-outs.
Technical Competencies
- Hardware Languages: Mastery of SystemVerilog and Verilog.
- Full-Flow Implementation: Comprehensive hands-on command of the RTL-to-GDSII flow (Logic Synthesis, Floorplanning, CTS, P&R, STA, and Physical Verification).
- EDA Tool Ecosystems: Deep proficiency with flagship EDA toolsuites from Synopsys (Design Compiler, IC Compiler II, PrimeTime) or Cadence (Genus, Innovus, Tempus).
- Scripting & Automation: Strong programming proficiency in Python, TCL, and Bash/Perl for methodology customization and CAD data manipulation.
- Post-Silicon Execution: Direct experience with actual silicon bring-up, hardware debugging, and lab evaluation.
Leadership & Soft Skills
- Strong mentorship capabilities with a track record of leveling up senior and mid-level engineering talent.
- Excellent written and verbal communication skills, with the ability to articulate highly abstract hardware complexities to non-technical stakeholders
Desired Experience and Skills- Master's or PhD degree in Electrical Engineering
- Prior experience with Power Management IC's
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The typical base pay range for this role across the U.S. is currently USD $122,900 - $255,200 per year. Starting base pay will depend on relevant experience and skills, training and education, business needs, market demands, the ultimate job duties and requirements, and work location. Skyworks has different base pay ranges for different work locations in the U.S. Benefits include access to healthcare benefits (including a premium-free medical plan option), a 401(k) plan and company match, an employee stock purchase plan, paid time off (including vacation, sick/wellness, parental leave), among others. Employees are eligible to participate in an incentive plan, and certain roles are also eligible for additional awards, including recognition and stock. These incentives and awards are based on individual and/or company performance.
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