B.S. + 10 years or M.S. + 7 years in Electrical Engineering, Computer Engineering, or related field
Strong fundamentals in digital communications and DSP, including probability/statistics
Practical experience in high-speed wireline DSP with focus on FFE/DFE, adaptation, CDR, and MLSD/Viterbi concepts
Expertise in FEC integration and fixed-point modeling
Proficient in C++ and MATLAB for algorithm development, modeling, and analysis
Responsibilities
Architect and simulate DSP signal chains for automotive Ethernet PHYs, defining features and performance targets
Implement DSP algorithms in Verilog/System Verilog while adhering to design specifications
Collaborate with algorithm and systems teams to define hardware architecture
Translate fixed-point MATLAB/C/C++ models into synthesizable HDL code
Design RTL for timing recovery and synchronization blocks, considering jitter tolerance
Contribute to detection and coding with integration of FEC, focusing on performance and complexity tradeoffs
Support silicon bring-up and lab debugging, correlating models to silicon and root-causing issues
Work collaboratively across teams to deliver implementable and testable solutions
Benefits
Opportunities for professional development and continuous learning
Access to state-of-the-art technology for automotive applications
Collaborative work environment with cross-functional teams
Support for silicon debugging and hands-on lab experience
Innovative projects in the rapidly evolving automotive sector
Full Job Description
Your Role
Key responsibilities in your new role
Architect and simulate DSP signal chains for automotive Ethernet PHYs: define features, performance targets, and algorithm specs for mixed-signal and digital teams
Implement DSP algorithms (e.g., Filtering, Error Correction coding, echo cancellation, receiver equalization, and so on) in Verilog/System Verilog, ensuring adherence to design specifications
Collaborate with the algorithm and systems teams to define hardware architecture
Translate fixed-point MATLAB/C/C++ models into fixed-point, synthesizable HDL code
RTL Design and implement timing recovery/synchronization blocks (CDR, tracking loops), including jitter tolerance and stability/latency tradeoffs
Contribute to detection and coding / FEC integration: soft-information interfaces, performance/complexity tradeoffs, and linkKPIs
Support silicon bring-up and lab debug: correlate model 14 silicon, root-cause issues, and iterate on algorithms/specs
Collaborate across architecture, design, verification, and applications to deliver implementable and testable solutions
Your Profile
Qualifications and skills to help you succeed
B.S. + 10 years (or M.S. + 7 years) in Electrical Engineering, Computer Engineering, or related field
Strong fundamentals in digital communications and DSP, including probability/statistics
Practical experience in high-speed wireline DSP, including some mix of: FFE/DFE, adaptation, CDR, MLSD/Viterbi concepts, FEC integration, fixed-point modeling
Strong C++ and MATLAB skills for algorithm development, modeling, and analysis
About Infineon Technologies
Infineon Technologies AG is a German semiconductor manufacturer that produces a wide range of products including microcontrollers, power semiconductors, and sensors. The company was founded in 1999 and is headquartered in Neubiberg, Germany. Infineon Technologies has a global presence with operations in Europe, Asia, and the Americas. The company's mission is to make life easier, safer, and greener with technology.
