Bachelor's degree in Electrical Engineering required; Master's preferred.
8+ years of experience in complex SoC/silicon product development.
Strong organizational skills with the ability to manage multiple tasks.
Entrepreneurial mindset with a customer-focused approach.
Authorized to work in the US and available to start immediately.
Responsibilities
Develop micro-architecture and implement front-end circuit design.
Conduct RTL design, synthesis, and IP integration.
Perform block-level verification for high-performance network controllers.
Drive full chip or block level ownership from architecture to GDS.
Utilize Synopsys and/or Cadence tools for digital design flows.
Benefits
Opportunity to work on cutting-edge networking technologies.
Collaborative and dynamic work environment.
Potential for professional growth and development.
Engagement in high-impact projects with significant customer interaction.
Full Job Description
Job Description
We are looking for Principal Design Engineers with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration, and block-level verification for high performance network controllers. The candidate must have good knowledge of communication/interface protocols such as PCI-Express (Gen-3 and above), Ualink, Esun, Ethernet etc.
Basic Qualifications:
Strong academic and technical background in electrical engineering. A Bachelor's degree in EE is required, and a Master's degree is preferred.
+8 years' experience supporting or developing complex SoC/silicon products for Switch ASIC, Networking applications and/or Server, Storage.
Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
Authorized to work in the US and start immediately.
Required Experience:
Hands-on, thorough knowledge of high-speed protocols like PCIe, Ualink, Esun, Ethernet, etc.
Proven front end design expertise - architecture, RTL, simulations, synthesis, timing closure, GLS, DFT etc.
Full chip or block level ownership from architecture to GDS, driving multiple complex designs to production
Experience with Synopsys and/or Cadence digital design tools/flows
Good knowledge of design for test (DFT), stuck-at and transition scan test insertion
Familiarity with UVM based design verification
Silicon bring-up and debug expertise
Small-geometry CMOS (6428nm) design
Preferred Experience:
Firmware development with C-language, scripting with Python or other equivalent programming languages.
Development/support for PCIe or Ethernet Switch products.
The base salary range is $185,000.00 USD - $240,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
About Astera Labs
Astera Labs is a semiconductor company that designs and develops purpose-built connectivity solutions for data-centric systems. The company's portfolio of products includes system-aware semiconductor integrated circuits (ICs), boards, and intellectual property (IP) that are used in data center servers, storage, and networking equipment. Astera Labs' products are designed to improve the performance, latency, and power consumption of data-centric systems. The company was founded in 2018 and is headquartered in Santa Clara, California.
