Responsibilities• Responsible for Physical Design tasks at block, sub-chip, and/or full-chip level incl. design planning, synthesis, placement, clock tree synthesis, custom clocking, static timing analysis, physical verification, IR drop & EM check and formal equivalence checks
• Responsible for delivering high-quality Electromigration and IR drop sign off modeling methodology and drive the overall EMIR convergence strategies
• To analyze and drive the Static Timing Analysis violations and its convergence
• To deliver best in class place and route (PNR) strategies especially on congestion and timing challenging blocks
• You are expected to be able to work with limited direction, have keen attention to detail, and be able to provide crisp status of progress, issues, and risks on the program to the management team. Occasional travel may be required
QualificationsRequired Qualifications: Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience OR equivalent experience.
Other Requirements:Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter. This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.
Preferred Qualifications: - Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
- OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience
- OR Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience
- OR equivalent experience.
- 4+ years of experience in Physical Design, especially in synthesis, place and route (PNR) and signoff
- 4+ years of hands-on experience in EDA vendor tools such as RHSC, Star-RC, Fusion Compiler, VCLP, Primetime, Formality, or Cadence Innovus and Conformal
Silicon Engineering IC3 - The typical base pay range for this role across the U.S. is USD $102,100 - $202,200 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $133,800 - $219,200 per year.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
https://careers.microsoft.com/us/en/us-corporate-pay
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.
