Responsibilities
Our team is building industry-leading, highly efficient, and scalable video codec hardware solutions (FPGA and ASIC) from the ground up to better serve billions of users. We are looking for strong video codec design engineers to design hardware accelerators for advanced video encoding and processing. The successful candidate will be part of a fast-growing team that includes algorithm, architecture, software, firmware, and hardware design and verification experts with a dedication to technical excellence and a passion to build large-scale and high-performing video platforms and services. Responsibilities: - Responsible for the hardware architecture design, architectural performance analysis, and optimization of key NPU modules in next-generation chips. - Responsible for performance modeling and analysis of emerging deep learning algorithms on chip systems; deliver inference performance for different models and assist in defining chip specifications such as compute throughput, bandwidth, and memory. - Responsible for architecture optimization targeting real-world application scenarios, achieving hardware-software co-optimization design. - Responsible for authoring architecture specification documents for key chip modules, and guiding the design implementation, optimization, and verification of the microarchitecture.
Qualifications
Minimum Qualification(s): - Master's degree or above in Microelectronics, Electronic Engineering, Integrated Circuits, Computer Science, or a related field. - Familiarity with Tensor Core; relevant experience in hardware acceleration for large language models. - Solid knowledge of computer architecture and digital integrated circuit design. - Familiarity with deep learning algorithms in areas such as large language models and CNNs. - Familiarity with distributed frameworks for large language model inference; understanding of how to compute the performance of AI model inference on chips. - Strong independent problem-solving skills, good communication and teamwork abilities, a strong desire to learn, the initiative to stay current with evolving trends in AI algorithms and chip architecture, and a forward-looking technical vision. Preferred Qualification(s): - Tape-out experience is a plus. - Familiarity with the architecture, protocols, and complex data flows of core SoC subsystems (e.g., CPU/NPU clusters, Memory subsystems, NoC). - Hands-on experience with Hardware Emulation (Palladium, ZeBu) or FPGA prototyping platforms. - Proficiency in Formal Verification methodologies and tools (e.g., JasperGold). - Experience in SoC-level Performance and Power-Aware (PA) verification.
Job Information
[For Pay Transparency]Compensation Description (Annually)
The base salary range for this position in the selected city is $162000 - $316800 annually.
Compensation may vary outside of this range depending on a number of factors, including a candidate's qualifications, skills, competencies and experience, and location. Base pay is one part of the Total Package that is provided to compensate and recognize employees for their work, and this role may be eligible for additional discretionary bonuses/incentives, and restricted stock units.
Benefits may vary depending on the nature of employment and the country work location. Employees have day one access to medical, dental, and vision insurance, a 401(k) savings plan with company match, paid parental leave, short-term and long-term disability coverage, life insurance, wellbeing benefits, among others. Employees also receive 10 paid holidays per year, 10 paid sick days per year and 17 days of Paid Personal Time (prorated upon hire with increasing accruals by tenure).
The Company reserves the right to modify or change these benefits programs at any time, with or without notice.
