Cadence Design Systems

Lead Software Engineer - Low-Power Verification

Cadence Design Systems$114K — $213K *
Information Technology
Less than 5 years of experience
Job Overview by Ladders

Qualifications

  • BS in CS, EE or related field with 4+ years' experience; MS with 2+ years; PhD with 1+ year or equivalent experience.
  • Working knowledge of IEEE 1801 UPF and RTL languages (Verilog, SystemVerilog, VHDL).
  • Ability to read, review, and reason about C++ code and object-oriented designs.
  • Scripting experience in Perl, Tcl/Tk, and/or Python.
  • Fluency with AI-assisted coding tools and ability to critically evaluate their output.

Responsibilities

  • Contribute to the UPF compilation flow by improving performance and reducing capacity.
  • Rebuild UPF documentation with valid examples to ensure alignment with coding standards.
  • Collaborate with R&D, PE, and AE teams to deploy UPF solutions across multiple key flows.
  • Help unify UPF compilation across Palladium and Protium platforms.

Benefits

  • Paid vacation and paid holidays.
  • 401(k) plan with employer match.
  • Employee stock purchase plan.
  • Variety of medical, dental, and vision plan options.
Full Job Description
Join our team and help build the next generation of low-power verification software for the Palladium and Protium emulation and prototyping platforms. As a Lead Software Engineer on the Palladium and Protium UPF R&D team you will be responsible for improving UPF compilation performance and correctness, adding support for new IEEE 1801 LRM revisions, and rebuilding UPF documentation around end-to-end workflows for multi-billion-gate low-power designs. What you will do • Contribute to the UPF compilation flow -- improve compilation performance, reduce instrumented capacity, and add self-checks across Parallel Partition Compiler (PPC) and Modular Compiler (MC) flows, including Dielet UPF support. • Rebuild UPF documentation around end-to-end compilation workflows, backed by valid SystemVerilog and UPF examples, and keep code and docs in sync through example-driven checks. • Work with R&D, PE and AE teams to deploy UPF solutions across key flows (AVIP, UVMA, MC, and Dielets -- each with UPF in 2- and 4-state). • Help consolidate and unify UPF compilation across Palladium and Protium. What we are looking for • BS in CS, EE, or a related field with 4+ years of experience; MS with 2+ years; PhD with 1+ year; or equivalent practical experience. • Working knowledge of IEEE 1801 UPF and RTL languages (Verilog, SystemVerilog, VHDL). • Ability to read, review, and reason about C++ code and object-oriented designs. • Scripting experience in Perl, Tcl/Tk, and/or Python. • Fluency with AI-assisted coding tools (Copilot, Claude, Cursor, or equivalent), with critical evaluation of AI output. • Strong technical writing skills - able to author user guides, specifications, and workflow-first documentation. The annual salary range for California is $114,800 to $213,200. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

About Cadence Design Systems

Cadence Design Systems, Inc. is an American multinational electronic design automation software and engineering services company, founded in 1988 by the merger of SDA Systems and ECAD, Inc. The company produces software, hardware and silicon structures for designing integrated circuits, systems on chips (SoCs) and printed circuit boards.
Learn more about Cadence Design Systems
Size
9,300 employees
Market Cap
$43.9 billion
Industry
Net Income
$590.6 million
Founded
2018
5 Year Trend
+10.5%
Revenue
$2.6 billion
NASDAQ

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