Cadence Design Systems

Lead Software Engineer - Low Power Verification

Cadence Design Systems$114K — $213K *
Telecommunications & Hardware
Less than 5 years of experience
Job Overview by Ladders

Qualifications

  • BS in CS, EE, or related field plus 4+ years experience; MS with 2+ years; PhD with 1+ year, or equivalent experience.
  • Familiarity with IEEE 1801 UPF and RTL languages (Verilog, SystemVerilog, VHDL).
  • Proven debugging skills including root-cause analysis from various logs and test cases.
  • Ability to read and analyze C++ code and object-oriented designs.
  • Experience with AI coding tools (e.g., Copilot, Claude, Cursor) and evaluating AI output.
  • Strong communication and technical writing abilities for developing user-facing documentation.

Responsibilities

  • Enhance UPF debug features for better usability in PPC and MC flows.
  • Scale UPF event logging and violation detection for complex low-power designs.
  • Rebuild UPF documentation for end-to-end debug scenarios backed by practical examples.
  • Develop AI-assisted UPF debug tools to streamline issue resolution.
  • Collaborate with R&D, PE, and AE teams to implement UPF solutions in key flows.
  • Consolidate UPF debug functionalities across Palladium and Protium.

Benefits

  • Paid vacation and holidays.
  • 401(k) plan with employer match.
  • Employee stock purchase plan.
  • Variety of medical, dental, and vision plans.
  • Additional unspecified benefits.
Full Job Description
Join our team and help build the next generation of low-power verification software for the Palladium and Protium emulation and prototyping platforms.

As a Lead Software Engineer - Low Power Verification you will be responsible for improving the performance and usability of UPF debug features, adding support for new IEEE 1801 LRM revisions, and rebuilding UPF documentation around end-to-end workflows for multi-billion-gate low-power designs.

What you will do:
  • Enhance UPF debug features -- improve performance and usability across the Parallel Partition Compiler (PPC) and Modular Compiler (MC) flows, including Dielet UPF support.
  • Scale UPF event logging and violation detection - apply new techniques to capture and report more UPF events, with better multi-billion-gate low-power designs.
  • Rebuild UPF documentation around end-to-end debug scenarios and workflows, backed by valid SystemVerilog and UPF examples.
  • Help develop AI-assisted UPF debug tools to reduce time-to-root-cause for low-power design issues.
  • Work with R&D, PE and AE teams to deploy UPF solutions across key flows (AVIP, UVMA, MC, and Dielets -- each with UPF in 2- and 4-state).
  • Help consolidate and unify UPF debug across Palladium and Protium.


What we are looking for
  • BS in CS, EE, or a related field with 4+ years of experience; MS with 2+ years; PhD with 1+ year; or equivalent practical experience.
  • Working knowledge of IEEE 1801 UPF and RTL languages (Verilog, SystemVerilog, VHDL).
  • Strong debugging skills - root-cause analysis from logs, waveforms, traces, testcases, and user reports.
  • Ability to read, review, and reason about C++ code and object-oriented designs.
  • Fluency with AI-assisted coding tools (Copilot, Claude, Cursor, or equivalent), with critical evaluation of AI output.
  • Strong communication and technical writing skills - able to turn scattered debug evidence into clear, user-facing workflows.

The annual salary range for California is $114,800 to $213,200. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

About Cadence Design Systems

Cadence Design Systems, Inc. is an American multinational electronic design automation software and engineering services company, founded in 1988 by the merger of SDA Systems and ECAD, Inc. The company produces software, hardware and silicon structures for designing integrated circuits, systems on chips (SoCs) and printed circuit boards.
Learn more about Cadence Design Systems
Size
9,300 employees
Market Cap
$43.9 billion
Industry
Net Income
$590.6 million
Founded
2018
5 Year Trend
+10.5%
Revenue
$2.6 billion
NASDAQ

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