Job Area:Engineering Group, Engineering Group > CPU Engineering
General Summary:Job DescriptionAs a CPU SRAM Design & Layout Engineer, you will be responsible for the design, analysis, implementation, and physical realization of high-performance custom SRAMs and register files. This role includes ownership of memory development from schematic capture and circuit design through layout implementation, verification, characterization, and model generation. You will collaborate closely with circuit design, CAD, and physical design teams to deliver high-quality memory solutions optimized for performance, power, area, and reliability.
Qualifications- Bachelor's degree in Electrical Engineering or related field with 5+ years of relevant industry experience
- OR Master's degree in Electrical Engineering with 2+ years of relevant industry experience
- Experience designing custom SRAM circuits and register files
- Experience with custom memory layout design and implementation
- Experience using industry-standard custom design tools and methodologies
- Experience with circuit simulation, Monte Carlo analysis, and static timing analysis
- Knowledge of advanced semiconductor technologies, including FinFET and nanosheet process nodes
- Experience with deep sub-micron layout design for memory, datapath, and standard cell circuits
- Knowledge of layout floorplanning, hierarchical assembly, and physical verification methodologies
- Experience with Cadence Virtuoso and Calibre LVS/DRC verification flows
Preferred Qualifications- Strong understanding of SRAM and register file architectures with advanced custom circuit implementations
- Strong understanding of high-performance and low-power circuit design techniques
- Strong knowledge of semiconductor device physics and reliability considerations
- Experience with variation-aware simulation methodologies in advanced technology nodes
- Experience with complete memory development flows, including:
- Design entry
- Functional verification
- Layout implementation and guidance
- Simulation and characterization
- Timing and power analysis
- Electrical characterization
- Deliverable model generation
- Good understanding of the impact of physical implementation on circuit performance, power, and area
- Experience with memory logical models (Verilog) and functional verification
- Experience with BIST and DFT methodologies
- Experience developing memory analysis flows and automation methodologies
- Knowledge of EMIR analysis and mitigation techniques
- Proficiency with tools such as NanoTime, Ansys EMIR, ESP-CV, and Liberate
- Experience writing SKILL code or other automation scripts for layout and design productivity
- Strong communication and collaboration skills
Roles and Responsibilities- Design and develop custom SRAM and register file circuits optimized for high performance, low power, and scalability
- Create schematics and perform circuit-level design and optimization
- Develop memory floorplans and custom layouts based on project requirements and schematics
- Own memory implementation from initial architecture and floorplanning through physical verification and signoff
- Perform and oversee layout construction, verification, and optimization
- Read and interpret process design rules to create robust, manufacturable layouts
- Execute and analyze LVS, DRC, ERC, and other physical verification checks
- Identify and resolve design, verification, and layout issues throughout the development process
- Perform functional verification, simulation, and margin analysis across process, voltage, and temperature conditions
- Perform timing, power, and electrical characterization of memory designs
- Generate and validate all required memory deliverables and collateral models
- Collaborate with CAD teams to improve modeling, automation, and characterization flows
- Work with Physical Design teams to resolve memory PPA (Power, Performance, Area) challenges
- Provide layout guidance and physical implementation recommendations to improve circuit performance, reliability, and manufacturability
- Contribute to DFT, modeling, automation, and analysis flow development where applicable
- Develop realistic project schedules and independently drive memory design and implementation activities to completion
- Provide technical insight and recommendations regarding memory architecture, layout strategy, area optimization, and methodology improvements
Minimum Qualifications:• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
OR
Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 1+ year of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
OR
PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.
Pay range and Other Compensation & Benefits: $147,900.00 - $221,900.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link.
If you would like more information about this role, please contact Qualcomm Careers.
