Bachelor's or Master's Degree in Electrical Engineering
Good understanding of synchronous hardware design concepts
Knowledge of VHDL language
Experience with Xilinx or Altera FPGA technologies
Recognized for superior learning abilities
Functional English proficiency (especially in writing)
Assets: Knowledge in modem/DSP technology, basic Linux commands, Matlab, System Verilog or object-oriented languages, and scripting languages like Perl and TCL.
Responsibilities
Analyze and understand the requirements for design and draft descriptions
Design and implement algorithms in VHDL
Perform necessary simulations using ModelSim
Collaborate with the verification specialist for effective debugging
Conduct synthesis and implementation testing
Provide management with project timelines and progress updates
Participate in design reviews and offer feedback
Benefits
Opportunity to work on cutting-edge FPGA technology
Collaborative work environment with specialists
Engagement in iterative debug processes
Involvement in the design impact assessment through reviews
Full Job Description
RESPONSABILITÉS :
Analyser et comprendre les requis dans le but de faire de la conception et de rédiger la la description.
Concevoir et implémenter les algorithmes en VHDL.
Effectuer les simulations nécessaires avec ModelSim.
Travailler en étroite collaboration avec le spécialiste en vérification, afin d'effectuer efficacement la boucle itérative de debug/correction.
Effectuer des tests de synthèse et d'implémentation.
Participer aux révisions de conception et fournir des commentaires appropriés.
QUALIFICATIONS:
Bac ou Maitrise en Génie Électrique
Une bonne compréhension des concepts de conception matérielle synchrone
Connaissances du langage VHDL.
Connaissance des technologies de FPGA Xilinx ou Altera.
Reconnue pour sa capacité supérieure d'apprentissage.
Connaissance fonctionnelle de l'anglais (surtout en écriture).
Atouts:
Technologie de transmission hertzienne (Modem, DSP).
Commandes Linux de base, Script Linux.
Matlab.
System Verilog ou Langage Oriente Objet.
Connaissance de langage de script tell Perl, TCL.
RESPONSABILITIES:
Analyze and understand the requirements in order to design and draft the description.
Design and implement the algorithms in VHDL.
Perform the necessary simulations with ModelSim.
Work closely with the verification specialist to efficiently perform the iterative debug/correction loop.
Perform synthesis and implementation testing.
Provide management with timelines, project progress tracking and unplanned tasks.
Participate in design reviews and provide appropriate feedback.
QUALIFICATIONS:
Bachelor's or Master's Degree in electrical engineering.
A good understanding of synchronous material design concepts.
Knowledge of VHDL language.
Knowledge of Xilinx or Altera FPGA technologies.
Recognized for his/her superior learning skills.
Functional knowledge of English (especially written).
