Cisco

ASIC Technical Leader - Product Quality & Productization (Hybrid)

Cisco$214K — $309K *
Telecommunications & Hardware
15+ years of experience
Job Overview by Ladders

Qualifications

  • 20+ years in Silicon DFT, Test, Quality, and Program Management; at least 5 years in high-reliability hardware environments.
  • In-depth knowledge of ASIC development lifecycle, particularly in Silicon One and advanced FinFET processes (6nm/7nm).
  • Proficient in Synopsys tools (Design Compiler, Tetramax, Spyglass, VCS) and ATE (93K testers).
  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or similar.
  • Expertise in Statistical Process Control (SPC) and software tools (JMP, Python, SQL) is a plus.

Responsibilities

  • Direct development and execution of DFT architectures (JTAG, SCAN, BIST) at top-level RTL.
  • Guide teams on integrating DFM and DFT principles in early development for optimal test coverage.
  • Oversee the transition of SoC products from development through mass production.
  • Manage program risks and report on manufacturing health and yield optimization.
  • Lead Root Cause Analysis initiatives using advanced diagnostics for corrective actions.
  • Supervise product qualification processes including Environmental Stress Screening and life testing.
  • Monitor manufacturing data to optimize processes and improve yields.

Benefits

  • Hybrid work model (3 days in office in San Jose, California).
  • Opportunity to influence high-level technical partnerships in the silicon industry.
  • Engagement in the end-to-end product lifecycle, enhancing career breadth.
  • Access to advanced diagnostic tools and methodologies.
  • Work in a high-reliability hardware environment, broadening experience in cutting-edge technology.
Full Job Description
The application window is expected to close on: 09/03/2026
Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.

This position is a hybrid position with approximately 3 days in office in San Jose, California, United States.

Your Impact

This position provides high-level technical leadership for the Silicon One organization, bridging the gap between advanced DFT architecture, silicon quality, and high-volume manufacturing. The role is responsible for the end-to-end product lifecycle-from RTL design and NPI through mass production-ensuring that our programmable silicon architecture maintains the highest industry standards for reliability, yield, and field performance. Responsibilities include:

DFT Strategy & Implementation
  • Direct the development and execution of robust DFT architectures (JTAG, SCAN, BIST) and integrate test modes at the top-level RTL.
  • Guide multi-functional teams in integrating Design-for-Manufacturability (DFM) and DFT principles early in the development cycle to ensure optimal test coverage.


NPI & Mass Production Leadership
  • Orchestrate the transition of complex SoC products from development through New Product Introduction (NPI) to successful mass production.
  • Manage program risks and provide executive-level status reporting on manufacturing health and yield optimization.


Quality & Reliability Engineering
  • Lead high-level Root Cause Analysis (RCA) initiatives, using advanced diagnostics to drive corrective and preventative actions.
  • Supervise comprehensive product qualification, including Environmental Stress Screening (ESS), electrical characterization, and accelerated life testing.
  • Implement advanced yield analysis, power binning, and fuse array repairs to drive DPPM to industry-leading lows.


Data-Driven Process Optimization
  • Monitor high-volume manufacturing data to identify trends, optimize process windows, and drive continuous yield improvement.
  • Ensure adherence to global quality standards (ISO 9001) and maintain comprehensive technical documentation for all quality plans.


Minimum Qualifications
  • 20+ years in Silicon DFT, Test, Quality, and Program Management; minimum of 5 years specifically within high-reliability hardware environments.
  • Deep knowledge of the full ASIC development lifecycle, specifically within the Silicon One pipeline and advanced FinFET processes (6nm/7nm).
  • Mastery of Synopsys suite (Design Compiler, Tetramax, Spyglass, VCS) and ATE (93K testers).
  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related technical field.


Preferred Qualifications
  • Data Analytics: Validated expertise in Statistical Process Control (SPC) and diagnostic tools (JMP, Python, SQL).
  • Leadership: Proven success in leading multidisciplinary teams, influencing high-stakes technical partnerships, and translating complex data into actionable executive insights.

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Industry
Net Income
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Founded
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5 Year Trend
+1.4%
Revenue
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