ContextAs chip sizes increase and packaging technologies become more complex, substrate engineering is emerging as a critical domain. This role supports TSMC's leadership in 3DIC and advanced packaging by extending expertise beyond chip-level design into package-level integration. The team is addressing challenges such as warpage, power delivery, thermal management, and material innovation. Future evolution includes Chip-on-Wafer-on-PCB (CoWoP) under TSMC's System Technology Optimization program.
The position requires strong design and technology expertise to define future customer requirements, focusing on integrated packaging (IP), dielectric parameters, high-speed I/O, and trade-offs that directly impact system performance. This role is critical in shaping the direction of 3DIC development.
OverviewWe are seeking a highly skilled and motivated Substrate / Advanced Package Engineer to join our cutting-edge 3DIC design team. The ideal candidate will have a strong foundation in semiconductor physics, mechanical engineering principles, and EDA (Electronic Design Automation) tools, with a passion for innovation in advanced package design. The role involves design, simulation, and modeling of complex substrate and packaging technologies to support next generation 3DIC applications.
Responsibilities- Design, simulate, and optimize advanced packaging for 3DIC applications.
- Collaborate with cross-functional teams to define specifications and requirements.
- Perform modeling of warpage, stress, reliability, and thermal performance using industry-standard EDA tools.
- Formulate and solve problems in research-driven, often ambiguous domains.
- Provide guidance on high-speed I/O modeling and integration.
- Develop and maintain documentation, including specifications, test plans, and design reviews.
Stay current with industry trends, tools, and technologies in advanced packaging.
Requirements- Master's degree or Ph.D. in Electrical Engineering, Mechanical Engineering, or a related field.
- 15+ years of hands-on expertise in advanced packaging technologies and substrate design.
- Understanding of semiconductor device physics and packaging process technologies.
- Strong knowledge of warpage, stress, and thermal effects in packaging.
- Proven ability to drive solutions in ambiguous, research-oriented contexts.
- Excellent problem-solving, analytical, and communication skills.
- Strong collaboration skills, with the ability to mentor junior engineers.
- Ability to balance strategic insight with hands-on technical execution.
Preferred Skills- Experience with reliability, IR/EM, and multi-physics analysis.
- Familiarity with machine learning techniques for design optimization.
- Patents, publications, or demonstrated innovation in substrate or packaging domains.
Success Metrics- Ability to provide impactful, data-driven suggestions that influence design direction.
- Effective use of modeling and simulation to validate proposals.
- Establishing trust and credibility with global teams.
- Enabling adoption of new technologies within the 3DIC ecosystem.
Location- San Jose, CA or Hsinchu, Taiwan.
Date: Sep 13, 2026
Country/Region: US
City: San Jose
Company: TSMC Technology, Inc.
