Deep expertise in computer architecture and micro-architecture, particularly for accelerators or domain-specific architectures.
Strong performance modeling and analysis skills, with experience in analytical or simulation-based models.
Experience profiling and optimizing deep learning workloads on hardware accelerators (GPUs, TPUs, ASICs, FPGAs).
Understanding of hardware/software co-design principles and cross-layer optimization.
Solid foundation in digital circuit design and its impact on performance.
Experience with reconfigurable or heterogeneous architectures.
Ability to quantitatively assess performance bottlenecks across all system layers.
Responsibilities
Develop performance models for Sohu's transformer architecture across various workloads.
Profile deep learning workloads to identify and address micro-architectural bottlenecks.
Build analytical models to predict performance of different architectural configurations.
Collaborate with hardware architects to guide micro-architectural decisions.
Drive opportunities for hardware/software co-optimization to improve performance.
Optimize memory hierarchy performance and resource efficiency.
Develop benchmarking frameworks specific to transformer inference workloads.
Benefits
Full medical, dental, and vision coverage with generous premiums.
Housing subsidy of $2,000/month for employees within walking distance.
Daily lunch and dinner provided in-office.
Relocation support for new hires moving to West San Jose.
Full Job Description
Key responsibilities
Develop comprehensive performance models and projections for our architecture across varying workloads and configurations
Profile and analyze deep learning workloads on our hardware to identify micro-architectural bottlenecks and influence optimization opportunities
Drive hardware/software co-optimization by identifying where architectural features can unlock performance improvements
Run regressions and validate performance models against real systems and silicon
Inform next-generation architectural decisions by pathfinding across system and silicon options during design, proof-of-concept, and architecting phases
You may be a good fit if you have at least one of the following:
Strong performance modeling and analysis skills with experience building analytical-based or simulation-based performance models
Solid understanding of computer architecture and micro-architecture, particularly for accelerators
Experience profiling and analyzing deep learning workloads on hardware accelerators (GPUs, TPUs, ASICs, FPGAs, or others)
Solid software engineering fundamentals with an eye toward auditability and maintainability
Strong candidates may also have
Deep knowledge of GPU architectures and/or programming models like CUDA
Experience mapping models to multi-chip inference systems
Familiarity with transformer model architectures and inference serving optimizations
Experience with architecture simulators and performance modeling tools (gem5, trace-driven simulators, custom models)
Exposure to ASIC, FPGA, or CGRA-based accelerator development and hardware/software co-design principles
Published research in computer architecture, ML systems, or hardware acceleration
Benefits
Medical, dental, and vision packages with generous premium coverage
$500 per month credit for waiving medical benefits
Housing subsidy of $2k per month for those living within walking distance of the office
Relocation support for those moving to San Jose (Santana Row)
Various wellness benefits covering fitness, mental health, and more
Daily lunch + dinner in our office
Unlimited compute budget subject to ROI justification
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.
