BS or MS in Electrical Engineering, Computer Engineering, or a related field.
10+ years of experience in STA and timing closure at tier 1 design houses.
Proven track record in closing timing at advanced process nodes.
Hands-on experience with commercial synthesis and timing tools like Design Compiler and Fusion Compiler.
Deep understanding of STA, Liberty formats, and device characterization.
Background in device physics at advanced nodes.
Experience with die-to-die or chiplet-to-chiplet timing closure.
Familiarity with timing closure on 3D ICs, including TSV design.
Responsibilities
Design timing closure strategies for large-scale designs and 3D ICs with the R&D team.
Execute backend and timing flows with customers to gather insights for product improvement.
Communicate customer feedback to research and product teams to influence priorities.
Serve as the in-house expert on STA and timing closure.
Collaborate with customers to refine product architecture.
Benefits
Unlimited PTO and comprehensive benefits (medical, vision, dental, 401k).
Two engineering-focused offices with free parking and a private gym.
Free lunch, drinks, and snacks provided.
Full Job Description
Role Overview
We're hiring an STA/Timing ClosureLead to develop solutions for closing timing on multi-billion instance ICs and 3D ICsYou'll work with R&D to define the product architecture and refine the solution at our customer sites.
Key Responsibilities
Design our approach to timing closure for very large designs and 3D ICs with the R&D team.
Run backend and timing flows with customers and use what you learn to improve the product.
Share customer feedback with research and product teams to help set priorities.
Act as our in house expert on STA and timing closure.
Qualifications
BS or MS in Electrical Engineering, Computer Engineering, or a related field.
10+ years running STA and timing closure at a tier 1 design houses.
Experience closing timing at advanced process nodes.
Strong hands on experience with commercial synthesis and timing tools such as Design Compiler and Fusion Compiler.
Deep knowledge of STA, Liberty formats, and device characterization.
Background in device physics at advanced nodes.
Experience with die to die or chiplet to chiplet timing closure.
Experience closing timing on 3D ICs, including TSV design and interconnect timing.
Interest in working directly with customers and shaping the product.
Nice to Haves
Experience with the broader implementation flow, including place and route.
Experience using AI coding agents such as Claude Code, Codex, or OpenCode.
Scripting experience in Python, Tcl, or Makefiles.
Why ChipAgents
Use your timing expertise to build AI tools for some of the largest chips being designed today.
Work with a strong technical team and an advisory board of EDA veterans, with a product already used by real customers.
What We Offer
$180K/yr - $350K/yr base salary + equity. Open to above-scale compensation for exceptional candidates.
Unlimited PTO and full benefits (medical, vision, dental, 401k).
Two engineering-centric offices with free parking, private gym, and free lunch, drinks and snacks.
About SEMI
SEMI is a global industry association that represents companies involved in the manufacturing and supply chain of the electronics industry. The association was founded in 1970 and is headquartered in Milpitas, California. SEMI provides its members with networking opportunities, industry research, and advocacy on issues affecting the industry. The association also hosts industry events and conferences, including SEMICON West and SEMICON China. SEMI has offices and operations in North America, Europe, Japan, Korea, Taiwan, China, and Southeast Asia.
