5+ years of experience in hardware simulator development for ASICs or novel compute architectures
Proven track record of building effective debugging, tracing, or profiling tools
Strong understanding of systems and compiler interactions with hardware
Ability to adapt simulators in line with evolving hardware designs
Proficiency in C++ or Rust, with familiarity in Python for tooling
Responsibilities
Own the architecture and roadmap of the hardware simulator, ensuring accuracy and performance
Ensure the simulator's behavior is reliable for compiler and runtime engineers
Develop debuggers, tracers, and profilers that enhance bug-fixing efficiency
Collaborate with Design Verification teams to align simulator outputs with hardware prototypes
Create benchmarks and traces from LLM inference workloads to validate simulator fidelity
Make informed decisions on simulator fidelity, speed, and tooling investments
Benefits
Flexible work environment
Opportunity to lead innovative projects in cutting-edge technology
Collaborative team culture focused on continuous improvement
Access to professional development resources
Potential for involvement in open-source communities
Full Job Description
The Role
Normal's hardware runs the most memory-bound parts of large-model inference inside memory itself, rather than shuttling weights to a processor. The software that makes this programmable doesn't exist yet in any standard form. Nothing off the shelf simulates it, so the tool our compiler and hardware teams depend on to validate their work before silicon exists has to be built, not bought. As our Simulator & Debug Tools Lead, you will own that simulator, along with the debugging and profiling tools that integrate with our compiler.
This is a hands-on technical leadership role. Fidelity, speed, and tooling all compete for the same hours, and you will decide where those hours go, keeping the rest of the team honest about what the chip can actually do. What You Will Own
Simulator Architecture: Own the architecture and roadmap of our hardware simulator, including accuracy, performance, and coverage of new hardware features as they land. Success means compiler and runtime work never waits on hardware.
Behavioral Correctness: Make the simulator's behavior, state, and memory semantics trustworthy enough that compiler and runtime engineers can act on what it tells them.
Debug and Profiling Tools: Build the debuggers, tracers, and profilers engineers actually reach for, measured by how quickly the team can find and fix a bug.
Hardware Correlation: Partner with our Design Verification and bring-up teams to correlate the simulator with RTL, FPGA prototypes, and eventually silicon, and close the loop when they disagree.
Workload Benchmarks: Build simulator benchmarks and traces from LLM inference workloads, so fidelity is measured against what the chip actually needs to run.
Investment Tradeoffs: Decide where simulator fidelity, simulator speed, and tooling investment go, and explain those tradeoffs to the compiler and hardware teams.
What Makes You a Great Fit
Experience building or leading development on hardware simulators, cycle-accurate or functional, for ASICs or novel compute architectures
Tooling instincts: you have built debuggers, tracers, or profilers that other engineers actually adopted
Enough systems and compiler context to simulate the software stack running on the hardware, as well as the hardware itself
Comfort working where the hardware being simulated is still evolving, and the simulator has to evolve with it
Fluency in C++ or Rust for simulator performance, and familiarity with Python for tooling
Bonus Points
Experience with in-memory compute or other non-von-Neumann architectures
Experience building simulators that fed directly into architectural or compiler decisions, beyond post-hoc validation
Experience with open-source simulation, tracing, or hardware-tooling communities
Background spanning both pre-silicon simulation and post-silicon bring-up
