Position Summary:

We are looking for a NPU Architect for next generation SOCs. This is a highly visible hands-on role leading individual and team contributions to NPU sub-system architecture, interface, performance and power tradeoffs. Responsible for anywhere from early-stage architectural exploration, research work focusing on machine learning, defining new features, performance modeling, Hardware-Software co optimization.

Position Responsibilities:

• Propose innovative NPU Architectural and micro-architectural features to boost PPA (Performance, Power and Area) on various targeted workloads in next generation SOCs
• Perform high-level performance modeling/simulation and analysis of NPU features, applications, benchmarks, and complex uses case
• Develop cycle accurate and analytical NPU performance model and correlate with Silicon
• Deliver architecture/microarchitecture proposals and specifications to the design team and articulate them effectively across audiences ranging from hardware & software engineers to architecture community peers, and to technology leadership
• Analyzing benchmarks, application workloads, and performance simulation results for architecture and microarchitecture optimizations
• Map AI use cases to NPU.
• Optimize and co-design of SW and HW to develop new architectures for low power and high performance
• Collaborate across teams to bring architecture proposals to fruition across the SOC, Driver, OS and System through detailed documentation

Required Skills:

• Bachelor's, Masters or PhD degree in Electrical, Computer Science, related Science or equivalent combination of education, training and experience
• 14+ years of experience in NPU architecture & development
• Hands on experience in developing cycle accurate performance and functional models
• Good knowledge and hands on experience in in CNN and LLM models
• Proficient programming skills in Python, System C and/or C++
• Experience in ML frameworks (TensorFlow, PyTorch, ONNX)
• Experience in micro architecture of SoC, interface subsystems, logic modules
• Self-motivated problem-solver with an ability to work well in a team

Special Attributes:

• Experience in performance/power modeling using Platform Architect
• Experience in mapping AI use cases to IPs
• Experience with hardware memory managements units, prefetching or memory subsystems
• Experience with multi-core systems and memory coherency
• Experience in ML model optimization on GPU Architecture
• Highly motivated with good verbal and written communication skills

Our total rewards programs are designed to motivate and engage exceptional talent. The base pay range for roles at this level is listed below, but may be higher or lower in other states due to geographic differentials in the labor market. Within the base pay range, individual rates depend on a number of factors-including the role's function and location as well as the individual's knowledge, skills, experience, education and training. This is part of our comprehensive compensation package with annual bonus eligibility and generous benefits to help you live life well.

Base Pay Range

$203,700-$305,500 USD

Additional Information

Disclosure of Trade Secrets

Samsung has a strict policy on trade secrets. In applying to Samsung and progressing through the recruitment process, you must not disclose any trade secrets of a current or previous employer.

Essential Job Functions

This position will be performed in an office setting. The position will require the incumbent to sit and stand at a desk, communicate in person and by telephone, and frequently operate standard office equipment, such as telephones and computers.