Job descriptionTeam Credo is looking for a Senior Staff PHY RTL Design Engineer to join our mission to transform connectivity at scale. In this role, you will be responsible for the RTL architecture, design, implementation, and verification of advanced SerDes PHY Digital Signal Processing (DSP) blocks used in next-generation networking, AI, data center, and high-performance computing products. The ideal candidate possesses strong digital design fundamentals, hands-on RTL development experience, and a good understanding of high-speed SerDes architecture. This position will be onsite at our San Jose, CA HQ.
Base salary range is $160,000 - $250,000 a year. The base salary offer will depend on factors such as education, experience, training, skills, qualifications, and location. This position is also eligible for a discretionary bonus, equity and a full range of medical and other benefits.
QualificationsBasic Qualifications
- BS/MS/PhD in Electrical Engineering, Computer Engineering, or a related field, with eight or more years of digital design experience (or equivalent expertise for senior candidates).
- Strong RTL development skills using SystemVerilog, including fixed-point arithmetic RTL implementation.
- Experience designing high-speed communication or DSP hardware.
- Experience with the ASIC development flow (e.g., Lint, CDC/RDC, synthesis, timing analysis) and familiarity with EDA tools from Synopsys, Cadence, or Siemens.
- Strong debugging and problem-solving skills.
Preferred Qualifications
- Experience with high-speed SerDes standards such as PCIe and Ethernet, and an understanding of SerDes receiver and transmitter architectures.
- Understanding of DSP algorithms (e.g., LMS adaptation, timing recovery), with MATLAB or C/C++ modeling experience.
- Familiarity with Python or other scripting languages.
- Knowledge of mixed-signal PHY architecture and analog/digital interfaces, including experience with mixed-signal PHY simulations.
- Experience supporting silicon bring-up and post-silicon validation, with exposure to advanced process nodes (7nm, 5nm, 3nm, or beyond).
Job responsibilities- Define RTL micro-architecture for digital PHY and SerDes DSP functions.
- Develop synthesizable RTL for DSP blocks (FFE, DFE, adaptive equalization, CDR loops), working with system architects and algorithm teams to translate DSP algorithms into RTL.
- Optimize designs for performance, power, area, and latency.
- Verify DSP modules and debug functional issues; support synthesis, timing closure, CDC/RDC analysis, and DFT integration.
- Analyze silicon bring-up data with validation teams to resolve issues, and support PHY integration and system-level debugging.
