BS/MS in Electrical Engineering or Computer Science with 5+ years of ASIC design experience.
Strong grasp of digital logic design and synchronous/asynchronous interfaces.
Proficient in Verilog/SystemVerilog RTL design.
Knowledgeable in synthesis and static timing analysis.
Expertise in scripting languages like Python, Tcl, Perl, or shell is preferred.
Strong problem-solving and planning skills are essential.
Excellent communication and collaboration abilities are a plus.
Responsibilities
Design, implement, and debug complex logic blocks and integrate IPs from vendors.
Support front-end integration activities including Lint, CDC, synthesis, and ECO.
Participate in design and code reviews to ensure high quality.
Develop functional tests and testbenches, running RTL and gate-level simulations.
Collaborate with verification, DFT, and physical design engineers for successful tape-outs and chip validation.
Benefits
Eligible for discretionary bonuses and equity.
Comprehensive medical benefits offered.
Full range of additional benefits included.
Full Job Description
Job description
As a Senior Design Engineer, you will be responsible for all aspects of front-end ASIC design, including RTL implementation and verification of complex logic blocks. You will collaborate with PD, DFT, STA, and integration teams to ensure successful tape-outs and work closely with system teams for chip bring-up and validation.
Base salary range is $100,000 - $170,000 a year. The base salary offer will depend on factors such as education, experience, training, skills, qualifications, and location. This position is also eligible for a discretionary bonus, equity and a full range of medical and other benefits.
Qualifications
Basic Qualifications
BS/MS degree in Electrical Engineering or Computer Science, with five or more years of relevant ASIC design experience.
Strong understanding of digital logic design and complex synchronous/asynchronous interfaces.
Proficiency in Verilog/SystemVerilog RTL design.
Knowledge of synthesis and static timing analysis.
Preferred Qualifications
Expertise in scripting languages (Python, Tcl, Perl, shell).
Strong problem-solving and planning skills.
Excellent communication and collaboration abilities.
Job responsibilities
Design, implement, and debug complex logic blocks, and integrate complex IPs from internal and external vendors.
Support front-end integration activities such as Lint, CDC, synthesis, and ECO.
Participate in design and code reviews to ensure quality.
Develop functional tests and testbenches, and run RTL and gate-level simulations.
Work with verification, DFT, and physical design engineers to achieve successful tape-outs; bring up, validate, and debug chip features, and collaborate with software, firmware, and systems teams.
