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X In most instances, this position requires in-person interviews as part of the hiring process.
Minimum qualifications: - Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, a related technical field, or equivalent practical experience.
- 5 years of software engineering (e.g., C and Python).
- Experience with computer architecture concepts (memory hierarchies, roofline models, bandwidth versus compute bottlenecks, network topologies).
- Experience with software design for simulation, performance modeling, or scientific computing.
Preferred qualifications: - Master's degree or PhD in Computer Science, or a related technical field.
- Experience designing LLM-based agentic orchestration loops (e.g., autonomous tool calling, multi-turn reasoning, self-correcting execution) or applying AI to automated software engineering, hardware/compiler optimization, or simulation workflows.
- Experience with performance profiling tools, analytical roofline modeling, or architectural simulators.
- Knowledge of modern transformer architectures (Dense and MoE, long-context attention, speculative decoding) and distributed execution paradigms (SPMD, pipeline, tensor, and expert parallelism) across modern ML frameworks (e.g., JAX, PyTorch/XLA, or Pallas).
- Ability to bridge high-level model specifications with low-level hardware constraints (interconnect latency, SRAM caching, DMA scheduling).
About the jobAs a Software Engineer on the Performance Simulation team, you will design and develop simulation software and AI-driven platforms that model how AI workloads (e.g., Gemini, MoE thinking/reasoning models, long-context serving) execute on applicant hardware architectures.
Operating at the critical boundary between frontier ML models and future accelerator roadmaps, you will build and automate cycle-level and analytical performance estimators to project throughput, latency SLOs, and Perf/TCO across different silicon configurations (SRAM/HBM hierarchies, multi-dimensional ICI interconnects, optical switching, and specialized compute engines like SparseCore). You will integrate LLM-driven agentic workflows to automate sweep generation, parameter exploration, data retrieval, and bottleneck diagnosis-accelerating hardware/software decisions.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $174000 - $252000 (USD) 15% bonus target equity benefits
Learn more about benefits at Google .
Responsibilities - Design, build, and maintain scalable performance simulation frameworks to accurately evaluate training and serving metrics for next-generation TPU configurations.
- Model how future model architectures (e.g., Mixture-of-Experts, multi-head latent attention, hybrid sequence parallelism, sparse attention, and KV-cache compression) interact with architectural variables (e.g., SRAM capacity/bandwidth, HBM contention, ICI network topologies, and live failover mechanisms).
- Develop and integrate AI-agentic platforms and toolchains to automate simulator sweep setup, parameter sensitivity analyses, and data extraction over gigabytes of simulation sweeps-reducing analysis cycles from weeks to hours.
- Build analytical and optimization engines (e.g., Mixed-Integer Programming/MIP, simulated annealing, roofline estimation) to identify Pareto-optimal execution strategies (sharding, tensor placement, weight pinning, prefetching).
- Formulate clear, data-grounded performance projections and comparative studies (e.g., Iso-execution analysis, trade-off studies between compute density versus memory bandwidth) to inform multi-year TPU platform roadmaps and hardware contracts.
