Cadence Design Systems

Senior Software Architect

Cadence Design Systems • $210K — $390K *
Information Technology
8 - 10 years of experience
Job Overview by Ladders

Qualifications

  • MS in Computer Science or Electrical Engineering with 12+ years of experience, or PhD with 10+ years of experience.
  • 10+ years of experience in EDA software development.
  • Strong expertise in RTL/Logic Simulation and Timing Analysis, especially with SDC constraints.
  • Proficient in C/C++ with knowledge of SystemVerilog or Verilog.
  • Experience in multi-threaded/concurrent programming.
  • Quick learner able to adapt to new technologies.
  • Prior experience in RTL/logic simulation software development preferred.

Responsibilities

  • Enhance and support the Xcelium RTL/logic simulator engine.
  • Support Timing Constraints Verification technology in Xcelium.
  • Design, tune, and innovate graph algorithms for multi-billion-node graphs.
  • Conduct bottleneck analysis and implement optimizations in C/C++.
  • Lead junior engineers and collaborate with a global team.
  • Participate in technical discussions, code reviews, and process improvements.
  • Write specifications and unit tests for developed code.

Benefits

  • Paid vacation and paid holidays.
  • 401(k) plan with employer match.
  • Employee stock purchase plan.
  • Variety of medical, dental, and vision plan options.
Full Job Description

Join the team behind Xcelium, the industry-leading logic simulator, to architect the next generation of hardware verification technology. As a Senior Engineer in the System Verification Group, you will be at the forefront of EDA innovation, evolving the Xcelium simulator to meet the staggering complexity of future AI and hyperscale chip designs. You will be part of an innovative, geographically distributed team dedicated to advancing the capabilities of RTL/logic simulation for semiconductor technology. The work environment encourages collaboration, technical excellence, and continuous learning.

We are looking for experienced C++ software engineers who thrive on "impossible" scaling challenges and want to invent the algorithms that will power tomorrow’s silicon.

Responsibilities:

  • Enhance and support Xcelium RTL/logic simulator engine to add new features and extend existing features.
  • Enhance and support Timing Constraints Verification technology used inside Xcelium simulator.
  • The role involves designing, tuning, and innovating graph algorithms involving SDC constraints support on multi‑billion‑node graphs.
  • Conduct deep-dive bottleneck analysis and implement performance optimizations in C/C++ to improve compilation speed and memory footprint.
  • Lead junior engineers and collaborate with global team members to deliver high-quality results in a distributed environment.
  • Contribute to technical discussions, code reviews, and process improvements.
  • Write Specifications and Unit Tests for your code.

Position Requirements/Qualifications:

  • MS in Computer Science or Electrical Engineering with a minimum of 12 years of experience OR PhD with a minimum of 10 years of experience
  • 10+ years of experience in EDA software development.
  • Strong background in RTL/Logic Simulation, SDC constraints and Timing Analysis especially path exceptions handling in a STA tool.
  • Excellent programming skills in C/C++ and a deep understanding of SystemVerilog or Verilog.
  • Experience in multi-threaded/ concurrent programming.
  • Ability to quickly learn new technologies and adapt to project requirements.
  • Prior experience with RTL/logic simulation software development is an added plus.

The annual salary range for California is $210,000 to $390,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

About Cadence Design Systems

Cadence Design Systems, Inc. is an American multinational electronic design automation software and engineering services company, founded in 1988 by the merger of SDA Systems and ECAD, Inc. The company produces software, hardware and silicon structures for designing integrated circuits, systems on chips (SoCs) and printed circuit boards.
Learn more about Cadence Design Systems
Size
9,300 employees
Market Cap
$43.9 billion
Industry
Net Income
$590.6 million
Founded
2018
5 Year Trend
+10.5%
Revenue
$2.6 billion
NASDAQ

Similar Jobs

More Jobs at Cadence Design Systems

More Information Technology Jobs

Find similar Senior Software Architect jobs: