Minimum qualifications:- Bachelor's degree or equivalent practical experience.
- 5 years of experience with software development in one or more programming languages.
- 3 years of experience building and shipping technical products. Experience with the domain area of Generative AI and Large Language Models (LLM).
- 3 years of experience testing, maintaining, or launching software products, and 1 year of experience with software design and architecture.
Preferred qualifications:- Master's degree or PhD in Computer Science or related technical field.
- 1 year of experience in a technical leadership role.
- Experience developing accessible technologies.
About the jobIn this role, you will develop and apply state-of-the-art AI methods-including multi-turn agentic flows, reinforcement learning (RLVR, RLAIF, RLHF), and evolutionary search to chip design, collaborating closely with research and production silicon teams across Google.
As a part of the team, composed of research scientists, research engineers, and software engineers, has already delivered significant impact on real products and flagship Google silicon through foundational research breakthroughs. You will work in lockstep with hardware architects, RTL/DV engineers, and ML model developers to integrate cutting-edge research directly into production chips.
As a part of the AI-assisted chip design team, you will leverage Gemini to optimize the EDA life-cycle and significantly accelerate silicon development. You will solve complex challenges across all design stages, improve Gemini for silicon applications to streamline hardware design and verification, enhance efficiency, and reduce time-to-market.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $174000 - $252000 (USD) 15% bonus target equity benefits
Learn more about benefits at Google .
Responsibilities - Architect, build, and scale multi-turn agentic flows with Gemini and evolutionary workflows (e.g., AlphaEvolve) for improving chip design.
- Develop and curate LLM benchmarks for chip design to evaluate and advance frontier model capabilities.
- Leverage scalable evaluation and Reinforcement Learning (RL) post-training workflows to improve Gemini models for chip design.
- Build on the momentum of landmark AI-for-silicon breakthroughs, where our AI-driven RTL and logic optimization methods have delivered substantial power, performance, and area (PPA) improvements on flagship production chips, and help shape the future of the chip design industry.
- Use AI to solve some of the most complex tasks in automating chip design, such as spec-to-RTL generation, RTL optimization, RTL debugging, and automated Design Verification (DV).
