Job descriptionTeam Credo is seeking a hands-on verification engineer to contribute to digital design verification for our high-performance networking and interface IP portfolio. In this role, you will help architect scalable, reusable verification environments, support UVM testbench development, contribute to verification plans and coverage goals, and partner closely with design and architecture teams to deliver high-quality, production-ready silicon.
Base salary range is $92,000- $154,000 a year. The base salary offer will depend on factors such as education, experience, training, skills, qualifications, and location. This position is also eligible for a discretionary bonus, equity and a full range of medical and other benefits.
Qualifications- Seven or more years of relevant experience, with a bachelor's or master's degree in electrical and/or computer engineering and a strong track record of technical leadership in ASIC/SoC verification methodology and execution.
- Strong understanding of digital design concepts (state machines, data paths, FIFOs, clock-domain crossings, resets, low-power behavior, performance-sensitive architectures), with advanced debugging skills across RTL, testbench, waveforms, assertions, and regression failures.
- Expertise in SystemVerilog, UVM, constrained-random and assertion-based verification, and development of synthesizable and behavioral models with emphasis on configurability and reuse; experience with at least one major tool suite (Cadence, Mentor, or Synopsys) for simulation, lint, and synthesis.
- Strong automation and scripting skills in Python, Perl, Tcl, and shell for regressions, reporting, stimulus, and workflow optimization.
- Knowledge of networking protocols (802.3 Ethernet, PCIe, CXL), on-chip bus and interconnect protocols (AMBA: CHI, AXI, APB), and Forward Error Correction (FEC) algorithms; knowledge of AI workloads is a plus.
Job responsibilities- Define the end-to-end verification strategy and architect reusable, scalable UVM-based testbench frameworks for IP and subsystem-level verification, leading development of reusable components (agents, drivers, monitors, scoreboards, reference models, constrained-random stimulus).
- Translate architecture and functional specifications into verification plans, test scenarios, checkers, assertions, and coverage models, ensuring compliance with relevant standards and internal and external specifications.
- Own regression planning and execution, failure triage, debug, root-cause analysis, and sign-off criteria; drive functional and code coverage closure, identify verification gaps, and improve methodology for quality and efficiency.
- Partner with design, architecture, firmware, emulation, and post-silicon teams, reviewing microarchitecture for testability and observability and influencing design decisions that improve verification effectiveness and debug productivity; support critical product and field issues.
- Develop automation and scripting infrastructure for regressions, reporting, and stimulus generation; lead design and verification reviews, establish best practices, and mentor engineers; evaluate AI-driven verification techniques and streamline existing methodologies around AI-enhanced solutions.
