10+ years of hands-on ASIC engineering experience, particularly in VLSI/SoC chip physical design workflows.
Deep knowledge of EDA tools like Cadence/Synopsys, including Genus/DC, power analysis, and clock methodology.
Strong expertise in front-end optimization using standard EDA tools.
Experience in leading backend design teams with knowledge of clock trees, routing, DRC, LVS, and metal fill.
Understanding of STA analysis and constraints for block-level and full-chip timing analysis.
Bachelor's or Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related field.
Excellent analytical, written, and verbal communication skills for effective collaboration.
Responsibilities
Lead ASIC front-end physical design and engineering workflow development for generative AI products.
Guide and assist colleagues to enhance frontend physical design at both block and full-chip levels.
Drive the optimization and implementation of new frontend physical design workflows, including synthesis and power analysis.
Provide guidance for static timing analysis (STA) and ensure adherence to design constraints.
Collaborate closely with ASIC team members to understand and improve their workflows and EDA needs.
Innovate and improve scalable, reliable, high-performance systems and tools for ASIC chip design.
Engage in hands-on design, debugging, and optimization of complex technical challenges.
Benefits
Opportunity to work in a fast-paced, agile HPC development environment.
Collaborative culture with a focus on innovation and continuous improvement.
Hands-on role that allows for direct impact on product development.
Exposure to cutting-edge technologies in generative AI and ASIC design.
Supportive team environment with opportunities for professional growth.
Full Job Description
The Opportunity:
In this leadership role, you will lead ASIC front-end physical design and associated engineering workflow development for Tensordyne's multimodal generative AI inference acceleration products. As a valued senior member of our ASIC team, you will guide and assist your colleagues to help improve frontend physical design aspects at both the block level and full-chip within a fast-paced, agile HPC development environment that utilizes EDA tools from external companies like Cadence/Synopsys and as well as internally developed workflows. You will drive Tensordyne's optimization, implementation and exploration of new frontend physical design workflows (includes at a min. synthesis, formal checks, and power analysis, and provide guidance for STA) and technologies for the full ASIC chip design process. Your contributions will continuously innovate and improve scalable, reliable, high-performance systems and tools to enable the next generation of Tensordyne products. This is a hands-on role that's ideal for ASIC physical design experts who have a multi-disciplinary engineering background, along with a keen interest in generative AI, and a passion for designing, debugging, optimizing and finding creative EDA solutions to complex technical challenges. In this role, you will work very closely with your ASIC team members who are engaged in the design and verification of Tensordyne products, to understand and improve their workflows and EDA needs.
What you'll bring:
10+ years of hands-on ASIC engineering experience, that includes deep knowledge of VLSI/SoC chip physical design workflows, with EDA tools like Cadence/Synopsys (Genus/DC), power analysis, clock methodology, and other commonly used aspects of physical design flows
Strong physical design knowledge for front-end optimization using standard EDA tools
Experience leading and supporting backend design team with understanding of clock trees, routing , DRC, LVS, metal fill till artwork release.
Understanding of STA analysis and constraints for block level and knowledge of full chip timing analysis
Excellent analytical, written, and verbal interpersonal skills along with an ability to productively collaborate within a global engineering team that moves at a startup pace.
Bachelor's or Master's degree in Computer Science, Computer Engineering, Electrical Engineering or a related technical field
