Meta is seeking a Research Scientist for the AI & Systems Co-Design team. The candidate will have industry experience driving next-generation AI accelerator architecture through hardware/software co-design. As a member of the Meta Training and Inference Accelerator (MTIA) Co-Design team, you will leverage this expertise to influence accelerator development from workload characterization and performance modeling through micro-architecture definition to pre-silicon validation. Your work will directly shape MTIA's hardware roadmap by translating insights from production ML workloads (large language models, recommendation systems, generative AI) into architectural decisions that improve performance, power efficiency, and cost at hyperscale. You will collaborate closely with silicon design, ML infrastructure, and product teams to ensure that the hardware we build is purpose-fit for the AI workloads of tomorrow.
Responsibilities
Shape MTIA's architecture: Translate production ML workload insights into hardware design decisions that improve performance, power efficiency, and cost across Meta's next-generation AI accelerators
• Drive pre-silicon decision-making: Lead deep, data-driven analysis of hardware micro-architectures, building the performance models and benchmarks that inform silicon investment decisions
• Build evaluation infrastructure: Develop tooling and frameworks for comparative architecture studies, enabling rapid exploration of design trade-offs before committing to silicon
• Operate cross-functionally at scale: Drive large initiatives spanning silicon design, ML infrastructure, and product teams, ensuring hardware roadmap decisions are grounded in real workload needs
• Define the methodology: Establish use cases, benchmarks, and evaluation criteria that become the standard for how Meta assesses hardware architecture options
• Bridge ML and hardware: Apply deep knowledge of how ML infrastructure interacts with accelerator hardware, networking, and memory systems to drive novel architectural innovations
• Elevate the team: Mentor research scientists and engineers within the team and across partner teams, establish and uphold documented standards for technical rigor (e.g., code review, reproducibility, benchmarking methodology), and promote technical rigor and innovation grounded in production impact
Minimum Qualifications
• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field
• 7+ years of industry experience (or equivalent)
• Experience in one or more of the following: hardware/software co-design, AI accelerator architecture, systems for ML, high-performance computing, or performance modeling
• Experience with power, performance, and area (PPA) trade-offs in hardware micro-architecture design
• Understanding of modern ML workloads (large language models, generative AI) and how hardware architecture choices impact their performance at scale
• Experience contributing to at least one silicon tapeout, from architectural exploration through pre-silicon validation
• Experience with AI system design, including networking, host-to-device ratios, and power trade-offs
Preferred Qualifications
• Demonstrated ongoing AI skill development (e.g., prompt/context engineering, agent orchestration) and staying current with emerging AI technologies
• Experience adhering to and implementing responsible, ethical AI practices (e.g., risk assessment, bias mitigation, quality and accuracy reviews)
• PhD degree in Computer Science, Computer Engineering, or a related field
• Demonstrated ability to integrate AI tools to optimize/redesign workflows and drive measurable impact (e.g., efficiency gains, quality improvements)
• Experience with ML frameworks (e.g., PyTorch) and the full software stack from model training/inference down to hardware execution
• Track record of technical leadership: defining roadmaps, driving cross-team alignment, and mentoring engineers
• Published research at top venues (ISCA, MICRO, HPCA, ASPLOS, MLSys) or equivalent industry contributions
• Experience with end-to-end AI hardware systems or on-device algorithm, logic and architecture development with performance, power and area optimizations
• Experience with numerics optimization (quantization, mixed-precision, custom number formats) for ML inference/training
