BS or MS in Electrical Engineering or related field.
12+ years of ASIC implementation experience, ideally in networking or automotive sectors.
Strong background in mixed-signal SoCs with successful tape-outs in advanced process nodes.
Experience leading complex multi-processor SoC subsystems with bus fabrics and NoCs.
Hands-on expertise in lint, CDC, synthesis, formal verification, DFT, and STA flows.
Proficient in Verilog and SystemVerilog, with scripting skills in Perl or Python.
Experience integrating custom analog blocks into digital top levels.
Responsibilities
Lead full-chip ASIC implementation of a mixed-signal SOC controller.
Drive the P&R team for smooth netlist handoffs and timely P&R deliverables.
Participate in flow reviews with the P&R team to optimize PPA for all blocks.
Lead timing signoff for the post-P&R database.
Benefits
Health, dental, and vision insurance.
Flexible Spending Account (FSA) and Health Savings Account (HSA).
Paid Time Off (PTO) plus 14 paid company holidays.
401K plan with a 3% company contribution.
Stock options available.
Life insurance and disability coverage.
Full Job Description
Job Description:
Lumotive is seeking a Principal Lead ASIC Design Implementation Engineer to lead the design and implementation of our mixed-signal beam-steering ASIC controller. As a hands-on lead, you will own the overall ASIC implementation flow and work closely with the physical design and analog design teams to bring the controller from RTL to tape-out. We're looking for a seasoned, self-motivated leader with a thorough, detail-oriented approach who thrives in a multidisciplinary, fast-paced environment.
Responsibilities:
Lead full-chip ASIC implementation of a mixed-signal SOC controller, including integration of custom analog blocks at the digital top level.
Drive the P&R team to ensure smooth netlist handoffs and timely execution of P&R deliverables.
Participate in flow reviews with the P&R team to achieve the best PPA for all blocks.
Lead timing signoff for the post-P&R database.
Qualifications:
BS or MS in Electrical Engineering or a related field.
12+ years of experience in ASIC implementation, preferably in networking, wireless, display controllers, touch controllers, or automotive sensor communication.
Strong experience with mixed-signal SoCs and the ASIC flow, with multiple successful tape-outs in advance process nodes.
Experience leading full-chip development of complex multi-processor SoC subsystems with bus fabrics and NoCs.
Hands-on experience with lint, CDC, synthesis, formal verification, DFT, and STA flows, including writing timing constraints at block and full-chip level.
Expertise in Verilog and SystemVerilog, and proficiency in Perl, Python, or similar scripting languages.
Experience integrating custom analog blocks into a digital top level.
Excellent analytical, debugging, and problem-solving skills.
