Qualifications

• B.S. + 10 years or M.S. + 7 years in Electrical Engineering, Computer Engineering, or related field
• Strong fundamentals in digital communications and DSP, including probability/statistics
• Practical experience in high-speed wireline DSP with focus on FFE/DFE, adaptation, CDR, and MLSD/Viterbi concepts
• Expertise in FEC integration and fixed-point modeling
• Proficient in C++ and MATLAB for algorithm development, modeling, and analysis

Responsibilities

• Architect and simulate DSP signal chains for automotive Ethernet PHYs, defining features and performance targets
• Implement DSP algorithms in Verilog/System Verilog while adhering to design specifications
• Collaborate with algorithm and systems teams to define hardware architecture
• Translate fixed-point MATLAB/C/C++ models into synthesizable HDL code
• Design RTL for timing recovery and synchronization blocks, considering jitter tolerance
• Contribute to detection and coding with integration of FEC, focusing on performance and complexity tradeoffs
• Support silicon bring-up and lab debugging, correlating models to silicon and root-causing issues
• Work collaboratively across teams to deliver implementable and testable solutions

Benefits

• Opportunities for professional development and continuous learning
• Access to state-of-the-art technology for automotive applications
• Collaborative work environment with cross-functional teams
• Support for silicon debugging and hands-on lab experience
• Innovative projects in the rapidly evolving automotive sector