Deep expertise in power integrity for high-performance semiconductors and PDN design principles.
Proven experience in advanced packaging environments, including 2.5D/3D integration and chiplets.
Bachelor's in Electrical Engineering or related field with 10+ years experience, or Master's/PhD with 7+ years.
Hands-on proficiency with PI simulation tools such as Ansys and Cadence/Sigrity.
Strong understanding of chip-package-system interactions and related reliability failure mechanisms.
Demonstrated ability to lead complex, cross-functional programs globally.
Excellent communication skills for influencing stakeholders.
Responsibilities
Define and implement power integrity architectures for heterogeneous integration.
Perform full-stack power integrity analysis and optimization.
Model and simulate power delivery solutions using industry-leading tools.
Lead power integrity co-design with silicon, package engineering, and photonics teams.
Drive selection and qualification of advanced power components and collaborate on PDN processes.
Develop and refine power integrity methodologies tailored to AI accelerators and chiplet architectures.
Analyze and mitigate power-related reliability risks under dynamic AI workloads.
Own power integrity qualification and lab validation for production ramp.
Benefits
Collaborative work culture with cross-functional teams.
Opportunities for professional development and growth.
Engagement with cutting-edge technologies in AI and photonics.
Supportive environment fostering innovation and creativity.
Full Job Description
About the Role
Lumilens is revolutionizing AI compute infrastructure with next-generation photonic interconnects, enabling massive scale-out and scale-up architectures through co-packaged optics (CPO), near-packaged optics (NPO), high-density silicon photonics, and advanced heterogeneous integration.
We're looking for a world-class Senior / Principal Power Integrity Engineer to own and drive power delivery strategies across complex 2.5D/3D packages that integrate electrical ICs, photonic ICs, chiplets, and high-bandwidth memory. You'll architect robust, low-noise, high-efficiency PDNs that support extreme power densities, tight voltage margins, and ultra-high-speed signaling-critical for powering the world's largest AI clusters without compromising performance or reliability.
Key Responsibilities
Define and implement power integrity architectures for 2.5D/3D heterogeneous integration, including chiplet-based designs, interposer/substrate scaling, on-package voltage regulation, multi-rail PDN topologies, decoupling strategies, and power-aware thermal co-design.
Perform comprehensive full-stack power integrity analysis and optimization-from die-level IR drop and electromigration to package-level PDN impedance profiling, transient response, and system-level power delivery network (PDN) validation.
Model, simulate, and validate power delivery solutions using industry-leading tools (e.g., Ansys SIwave, HFSS, Cadence Sigrity, Apache RedHawk, Voltus, or equivalent) across silicon, interposer, substrate, and board interfaces.
Lead power integrity co-design with silicon design, package engineering, and photonics teams to optimize bump maps, power/ground grid layouts, TSV/RDL routing, on-die decoupling, and voltage regulator placement for minimal noise, IR drop, and EMI in CPO/NPO systems.
Drive selection and qualification of advanced power components (VRMs, capacitors, inductors, low-loss substrates, advanced TIMs) and collaborate with foundry/OSAT partners on PDN process capabilities, manufacturability, yield, and cost.
Develop and refine power integrity methodologies, design rules, and sign-off criteria tailored to high-performance AI accelerators, photonic transceivers, and chiplet architectures.
Analyze and mitigate power-related reliability risks, including electromigration, thermal-induced voltage droop, power sequencing, and long-term stability under dynamic AI workloads.
Partner with cross-functional teams (architecture, Si design, package design, system engineering, supply chain) to explore emerging technologies, influence roadmaps, generate proof-of-concepts, and protect IP that maximizes power efficiency and performance.
Own power integrity qualification, lab validation (using high-bandwidth scopes, VNAs, spectrum analyzers), correlation to simulation, and readiness for volume production ramp.
Required Qualifications
Deep expertise in power integrity for high-performance semiconductors, with strong knowledge of PDN design principles, frequency-domain analysis, transient response, on-chip/off-chip decoupling, IR drop/EM analysis, and noise mitigation techniques.
Proven track record leading power integrity efforts in advanced packaging environments, including 2.5D/3D integration, chiplets, silicon interposers/bridges, FOWLP, CoWoS, hybrid bonding, or similar technologies.
Bachelor's degree in Electrical Engineering, Physics, or related field + 10+ years relevant industry experience; or Master's/PhD + 7+ years related experience.
Hands-on proficiency with PI simulation tools (Ansys, Cadence/Sigrity, Keysight ADS, Apache/RedHawk, or equivalents) and correlation to silicon measurements.
Strong understanding of chip-package-system interactions, high-speed signaling impacts on PDN, power-aware design for AI/HPC workloads, photonic interconnects and optical engines, and reliability failure mechanisms (e.g., EM, TDDB under high current densities).
Demonstrated ability to lead complex, cross-functional programs across global teams, foundries, OSATs, and suppliers.
Excellent communication, presentation, and documentation skills to influence stakeholders and drive technical alignment.
Preferred Qualifications
Experience with power integrity in silicon photonics, CPO/NPO, photonic IC/laser integration, or high-bandwidth optical interconnects for AI accelerators. DTCO for 3D IC solutions
Prior work defining long-term PDN roadmaps and executing from concept through high-volume manufacturing in hyperscale AI or HPC environments.
Leadership in multi-supplier or multi-company power integrity initiatives with measurable impact on performance, efficiency, or cost.
Familiarity with signal integrity/power integrity co-optimization, high-speed SerDes, PCIe/CXL interfaces, HBM integration, or advanced memory subsystems.
Familarity with photonic and electrical IC foundry processes (BICMOS, Advanced node CMOS...etc)
Knowledge of board/system-level power delivery requirements and multi-physics considerations (thermal-electrical coupling).
Ability to influence senior engineering leaders across silicon architecture, package design, systems, and supply chain.
