Experience with assertions for design verification
Familiarity with regression infrastructure setup
Solid understanding of debug tools used in verification
Responsibilities
Ensure silicon correctness using UVM-based environments
Implement formal methods in silicon validation
Collaborate with machine learning and verification engineers
Develop simulation engines for edge cases
Test for robustness in corner case scenarios
Benefits
Opportunity to work with a world-class team backed by top investors
Access to cutting-edge technology in AI and hardware development
Engagement in groundbreaking research and development
Flexible work environment fostering creativity and collaboration
Potential for career growth in innovative tech industry
Full Job Description
About this Role We are building next- generation tools for silicon design by combining deep verification expertise with modern AI systems. As a Senior Verification Engineer, your role isn't just verifying chips but redefining how teams verify chips. If you want to build tools that scale with the new era of complexity in hardware, this role offers high ownership and direct impact on real-world chip development.
What You'll Do
Own verification strategy across multiple IP blocks and subsystems, from testbench
architecture to signoff.
Design and develop AI assisted workflows that accelerate verification, coverage closure, and debug.
Build reusable verification frameworks using SystemVerilog, UVM, Python and custom automation tooling.
Collaborate with ML and software teams to integrate AI models into existing DV environments.
Contribute to product direction by exploring how automation can reshape verification methodologies.
Work with customers in a forward deployed capacity when needed, translating real design challenges into product features.
Drive tapeout readiness with full accountability for quality metrics, regression health, and coverage targets.
Mentor junior engineers and help define best practices for next generation verification teams.
What Makes This Role Unique
Opportunity to influence the future of tooling and AI guided verification flows.
High ownership from day one including technical decisions, roadmap input, and customer interactions.
Exposure to both engineering and product thinking.
Fast- moving environment built for builders who take initiative rather than wait for direction.
Qualifications
4 to 6 years of hands-on verification experience.
Strong SystemVerilog and UVM skills with proven debug depth.
Familiarity with Python or similar scripting languages.
Curious mindset toward AI or automation in verification, even if not an expert yet.
Ability to work across domains and communicate clearly with software or ML teams.
Comfortable interacting with clients, architects, and leadership when needed.
Thrives in a high responsibility environment and enjoys creating solutions that did not exist before.
Bonus Skills
Experience with formal verification, co-simulation or stimulus generation frameworks.
Background in ML, LLMs, data pipelines, or tool development.
Previous involvement in customer facing or forward deployed engineering roles.
Demonstrated ability to build tools that others actually use.
