Do you want to be at the forefront of designing the next Ryzen, Threadripper or Epyc CPU? Join AMD at the forefront of CPU innovation. We9re looking for an experienced and creative microarchitect to design core clocking, reset, and power management IP for our next-generation processors. If you9re passionate about low-power design, firmware-hardware interaction, and delivering high-quality products, this role offers the chance to make a direct impact on AMD9s flagship CPUs. Key Responsibilities: 3 Design and develop microarchitecture for core clocking, reset, and power management IP in next-generation processors. 3 Collaborate with architecture, design verification, physical design, and firmware teams to integrate IP into the overall processor using cutting-edge process technologies. 3 Define specifications and documentation for IP microarchitecture and interfaces. 3 Implement RTL in Verilog/SystemVerilog optimized for timing, area, power, and performance. 3 Develop C/C++ firmware for IP initialization, configuration, and control; partner with firmware engineers to ensure seamless integration. 3 Perform RTL linting, clock domain crossing (CDC) analysis, and related checks for design correctness. 3 Work with verification to build comprehensive test plans and ensure functional correctness. 3 Debug complex RTL and firmware issues; drive resolution across cross-functional teams. 3 Participate in design reviews and contribute to continuous improvement of quality and efficiency. Minimum Qualifications: 3 MS in EE, ECE, Computer Engineering, or Computer Science, plus 5+ years of experience in RTL design and microarchitecture for processors or complex IP. 3 Proficiency in Verilog/SystemVerilog for RTL design and verification. 3 Strong C/C++ development experience, including embedded firmware for power management. 3 Solid understanding of digital design fundamentals: synchronous/asynchronous design, CDC, multi-voltage, and power-aware design. 3 Knowledge of low-power methodologies (clock gating, power gating, DVFS). 3 Proven debugging skills across RTL and firmware; effective communication and teamwork. Preferred Qualifications: 3 Experience with processor power management architectures (DVFS, P-state/C-state control, power-performance optimization). 3 Expertise in hardware/firmware interactions for power control, sequencing, and system-level flows. 3 Familiarity with clock distribution, clock gating, CDC methodologies, and reset design in complex SoCs. 3 Experience with power gating, retention, isolation, and multi-voltage domain design on advanced nodes. 3 Understanding of thermal management, power budgeting, throttling, and reliability considerations. 3 Background in design-for-debug and design-for-test (scan, ATPG, MBIST, silicon observability). 3 Validation experience across simulation, emulation, and silicon bring-up. Location: Santa Clara, CA, USA Work Authorization: This role is not eligible for visa sponsorship. Benefits offered are described: AMD benefits at a glance. This posting is for an existing vacancy.