As a Physical Design Engineer, you will translate RTL designs into optimized silicon implementations, working across floorplanning, placement, clock tree synthesis, routing, and signoff to deliver high-performance, power-efficient chips. In this role, you will collaborate closely with architecture, design, and verification teams to shape the physical implementation strategy for wearable and spatial computing devices that define the future of human connection.

Responsibilities

Lead physical implementation of complex blocks and subsystems from floorplanning through tapeout, including placement, clock tree synthesis, routing, and physical verification
• Define and drive physical design methodology, constraints, and flows to meet power, performance, and area targets for custom silicon in VR and AR products
• Perform static timing analysis and timing closure across multiple process corners and operating conditions
• Develop and optimize power delivery network strategies, including IR drop analysis and electromigration sign-off
• Collaborate with RTL designers and architects to provide physical design feedback that influences microarchitecture and floorplan decisions
• Partner with design verification and DFT teams to ensure physical implementation supports functional correctness and testability requirements
• Drive physical verification sign-off including DRC, LVS, and antenna checks in advanced process nodes
• Identify and resolve physical implementation bottlenecks related to congestion, timing, and power through iterative analysis and targeted optimization
• Contribute to the development and continuous improvement of internal physical design flows, scripts, and automation to increase team efficiency

Minimum Qualifications
• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• 6+ years of experience in physical design of complex digital ASICs or SoCs, including floorplanning, placement, CTS, routing, and sign-off
• 6+ years of experience with static timing analysis and timing closure in advanced process nodes (7nm or below)
• Experience with industry-standard physical design EDA tools such as Cadence Innovus, Synopsys ICC2, or equivalent
• Experience with physical verification flows including DRC, LVS, and antenna sign-off
• Experience with power analysis and power delivery network implementation, including IR drop and electromigration analysis

Preferred Qualifications
• Experience with physical design implementation tools such as Synopsys Fusion Compiler (including FusionPilot/ConfigAI for run analysis and TCL configuration), Cadence Innovus, StarRC, and PrimeTime
• Experience with physical design for low-power wearable or mobile SoCs, including multi-voltage domain and power gating implementation
• Experience developing and maintaining physical design automation scripts using Python or Tcl to improve implementation flows
• Familiarity with co-design methodologies that bridge RTL microarchitecture decisions and physical implementation constraints
• Experience with advanced node process design kits (5nm or below) and associated physical design challenges