Cadence Design Systems

Lead Functional Product Engineer, Power Analysis

Cadence Design Systems$114K — $213K *
Information Technology
Less than 5 years of experience
Job Overview by Ladders

Qualifications

  • Hands-on experience with Signoff power analysis (static and dynamic power)
  • Knowledge of power optimization techniques in synthesis
  • Working knowledge of UPF (Unified Power Format)
  • Proficiency in Verilog/SystemVerilog for design analysis
  • Understanding of digital design fundamentals
  • Experience with low-power design methodologies
  • Familiarity with Liberty (.lib) and SPEF formats
  • Scripting skills in Tcl, Python, or Shell

Responsibilities

  • Develop and maintain Signoff power analysis flows with R&D
  • Reproduce, debug, and resolve customer-reported issues
  • Deploy and validate power analysis tools at customer sites
  • Collaborate with customers to optimize power results
  • Contribute to flow automation and scripting
  • Document debug findings and flow guidelines

Benefits

  • Paid vacation and holidays
  • 401(k) plan with employer match
  • Employee stock purchase plan
  • Variety of medical, dental, and vision plan options
Full Job Description
We are looking for a skilled engineer to join our Power Analysis team, focused on developing, debugging, and deploying Signoff power analysis flows at customer environments.

Key Responsibilities
  • Closely work with R&D to develop and maintain Signoff power analysis flows including integration with synthesis and PnR stages
  • Reproduce, debug, and resolve customer-reported issues in power analysis tools and flows
  • Deploy and validate power analysis tools at customer sites; provide hands-on technical support
  • Collaborate with customers to optimize power results and improve flow efficiency
  • Contribute to flow automation and scripting for repeatable deployments
  • Document debug findings, best practices, and flow guidelines
Required Skills
  • Hands-on experience with Signoff power analysis (static and dynamic power)
  • Knowledge of power optimization techniques in Synthesis (clock gating, operand isolation, multi-Vt cell selection,
  • Working knowledge of UPF (Unified Power Format) - power domains, isolation, level shifting, retention
  • Proficiency in Verilog/SystemVerilog for design analysis and testcase creation
  • Understanding of digital design fundamentals - clock domains, pipeline stages, timing/power trade-offs
  • Experience with low-power design methodologies (DVFS, power gating, multi-voltage)
  • Familiarity with Liberty (.lib) and SPEF formats
  • Scripting skills: Tcl, Python, or Shell
  • Familiarity with tools such as Joules, Voltus, PTPX or equivalent
Education & Experience
  • B.E./B.Tech or M.E./M.Tech in Electronics / VLSI / Computer Engineering or equivalent
  • Must have 3+ years of industry work experience

The annual salary range for California is $114,800 to $213,200. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

About Cadence Design Systems

Cadence Design Systems, Inc. is an American multinational electronic design automation software and engineering services company, founded in 1988 by the merger of SDA Systems and ECAD, Inc. The company produces software, hardware and silicon structures for designing integrated circuits, systems on chips (SoCs) and printed circuit boards.
Learn more about Cadence Design Systems
Size
9,300 employees
Market Cap
$43.9 billion
Industry
Net Income
$590.6 million
Founded
2018
5 Year Trend
+10.5%
Revenue
$2.6 billion
NASDAQ

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