12+ years of hands-on experience in physical implementation and signoff at 7nm and below, with multiple successful tapeouts.
Demonstrated expertise in digital synthesis, place-and-route, static timing analysis, and AI in EDA.
Strong debugging skills to efficiently isolate and resolve critical design issues.
Proficiency in scripting for automation and flow customization using languages like TCL, PERL, and Python.
Bachelor's or Master's in Electrical/Computer Engineering.
Responsibilities
Lead technical strategy and execution for critical customer design projects at advanced nodes (3nm and below).
Partner with sales teams to showcase Cadence's leadership in digital implementation and grow business.
Serve as a primary consultant for advanced-node design synthesis and implementation, leveraging deep expertise in key areas.
Develop and deploy custom solutions using scripting languages to meet unique customer requirements.
Mentor and guide junior engineers, fostering technical excellence and knowledge sharing.
Benefits
Paid vacation and paid holidays.
401(k) plan with employer match.
Employee stock purchase plan.
Variety of medical, dental, and vision plan options.
Full Job Description
Job Description Summary
The Senior Principal Application Engineer will be a trusted technical leader, driving complex pre-sales and post-sales engagements for Cadence Digital IC products at advanced nodes. This role demands a proven ability to solve the toughest design challenges and deliver innovative solutions that ensure customer success.
Key Responsibilities
Lead technical strategy and execution for critical customer design projects, influencing design methodologies and implementation flows at advanced nodes (3nm and below)
Partner with sales teams to grow Cadence business by showcasing Cadence's leadership in digital implementation.
Serve as a primary consultant for advanced-node design synthesis & implementation, Agentic-AI and signoff, leveraging deep expertise in synthesis, place & route, CTS, floor planning, timing signoff, design convergence with timing closure, and power optimization as key aspects.
Develop and deploy custom solutions using scripting languages (TCL, PERL, Python) to address unique customer requirements.
Mentor and guide junior engineers, fostering technical excellence and knowledge sharing across teams.
Requirements
12+ years of hands-on experience in physical implementation and signoff at 7nm and below, with multiple successful tapeouts.
Demonstrated expertise in digital synthesis, place-and-route, static timing analysis, AI in EDA, and achieving timing and power goals for advanced node designs.
Strong debugging skills with the ability to isolate and resolve critical design issues efficiently.
Proficiency in scripting for automation and flow customization.
Bachelor's or Master's in Electrical/Computer Engineering.
Exceptional communication and leadership skills, with a track record of building
The annual salary range for California is $148,400 to $275,600. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
About Cadence Design Systems
Cadence Design Systems, Inc. is an American multinational electronic design automation software and engineering services company, founded in 1988 by the merger of SDA Systems and ECAD, Inc. The company produces software, hardware and silicon structures for designing integrated circuits, systems on chips (SoCs) and printed circuit boards.
