Qualifications

• 5+ years of FPGA development experience or Master's/PhD in Computer/Electrical Engineering with 3 years of industry experience.
• Strong Verilog development skills with experience in Git-based repository management.
• High proficiency in FPGA placement, routing, timing closure, and simulation.
• Familiarity with network protocols like TCP and RoCE, and experience with debugging tools such as Wireshark.
• Basic understanding of network switch environments, with a capacity to learn about Arista and Juniper systems.
• Experience in AI-augmented development environments.

Responsibilities

• Lead the design and architecture of the full chassis-to-wafer IO system.
• Enhance current RTL designs and implement next-gen FPGA solutions.
• Generate production-ready bitstreams for deployment in large AI clusters.
• Collaborate with the DV team to minimize bugs and simplify debugging processes.
• Optimize FPGA datapaths for improved bandwidth and latency across all IO interfaces.
• Assist the board team in executing board bring-up procedures.
• Conduct debugging for network performance in extensive AI cluster environments.
• Incorporate cutting-edge networking technologies and protocols into designs.
• Manage cross-functional projects, ensuring effective integration of hardware and software components.

Benefits

• Engagement in cutting-edge AI and networking technology development.
• Opportunity to work on multiple generations of hardware systems.
• Collaboration with diverse technical teams across various disciplines.
• Exposure to leading networking technologies and hands-on FPGA work.
• Possibility to influence future generation architecture designs.