About The RoleThe Host and Network IO Team develops the full IO path implementation between a distributed system of server nodes, through the cluster, down to the custom RoCE network stack implemented in Cerebras' system, and over the proprietary IOs onto the WSE. As an FPGA developer on the team, you will own the in-chassis IO subsystem consisting of i) several cluster-facing RoCE v2 network interfaces via a custom implementation of the RDMA protocol; ii) a large programmable switching fabric; and iii) Serial IO communication with the Cerebras WSE via a proprietary protocol. You will interface between AI application-level IO teams, cluster architecture teams, and embedded software teams to develop solutions that optimize bandwidth and latency while minimizing congestion, pauses, pause spreading, unfairness, etc. The scope of work spans multiple generations of hardware products from improvements to presently deployed hardware, implementation of upcoming systems, and design/architecting of future next-gen architectures.
Responsibilities- Lead full chassis-to-wafer IO architecture and design
- Improve current RTL, implement next-gen FPGA design, define future IO architectures
- Produce production-ready bitstreams for deployment into large clusters running customer inference services
- Work with DV team to prevent bug slips and simplify debug
- Optimize bandwidth/latency over FPGA datapath and all IO interfaces
- Interface with board team facilitating and executing board bringup
- Drive network performance debug of large AI clusters
- Integrate leading edge networking technologies and protocols
- Lead cross-functional technical projects spanning multiple teams and integrating diverse software and hardware components to deliver an improved network IO solution.
- Foster clear and effective communication across teams and stakeholders.
Skills & Qualifications- 5+ years industry experience generating production FPGA solutions, OR Master's/PhD in Computer or Electrical Engineering + 3 years industry experience,
- Proficiency in Verilog development in Git based repo
- Highly productive with FPGA placement & routing, timing closure, simulation, debug, and other FPGA tools/workflows
- Network protocol familiarity (TCP, RoCE) and network debug tools such as Wireshark
- Knowledge of network switch environments or willingness to learn (Arista, Juniper, etc.).
- AI-augmented development environment
