Full Job Description
Broadcom's Central Engineering Design Correlation team is looking for an energetic and self-driven professional to join our team to help with silicon technology evaluation in advanced process nodes for IP and product designs. Our mission is to assess foundry technology offerings, help define new technology platforms for IP and product designs, risk assessment, and provide Broadcom's design communities with insights into design and process-technology interactions especially during co-development in advanced process nodes.
The candidate will have the opportunity to participate in new technology platform definition, PPAC (power performance area cost) assessment and benchmarking, test structure design, silicon characterization and model to silicon correlation in most advanced foundry technology nodes. The candidate will work closely with other experts in the fields of CMOS process technology, device & modeling, process and device reliability, digital & analog IP design, design sign-off flow for timing and power, CAD & EDA tools, as well as chip designers from various product lines. Primary duties will include assessment of technology offerings and capabilities to meet design needs and drive alignment with IP/product requirements. This role will involve active participation with foundry and internal teams on new technology enablement including help ensuring robustness of technology platforms.
Candidate must have the ability to prioritize well, communicate clearly, deliver solutions on time, and possess excellent data analysis & foundry interaction skills. The candidate expected to work across multiple facets of projects and juggle multiple responsibilities at the same time. The position is in Broadcom's Irvine facility in California.
Responsibilities:
Candidate will support IP and Chip teams with technology evaluation including reliability and design enablement. Responsibilities as part of technology evaluation will involve test structure layout, verification, extraction, simulation, and silicon evaluation.
The job scope will include a) cross-functional quality assurance of designs and tape-outs, b) EDA & RCX tool quality and predictability, and c) custom device infrastructure readiness & robustness.
Candidate will engage in collaborative team projects involving design, platform technology, and operations teams and foundry partner
Qualifications:
Degree in Electrical Engineering, Materials Engineering, Engineering Physics or related field with 8+ years of related experience after BS or 6+ years after MS or 3+ years after PhD with recent work in advanced FINFET (or GAA) nodes.
1. Strong background in advanced CMOS technology (FEOL, MEOL, BEOL) including understanding of design-technology interactions
2. Proficient in interacting with design teams and foundry partner
3. Familiarity with analog and digital design flows and CAD tools
4. Hands-on experience with device/circuit level test structure designs, verification (DRC, LVS), extraction, spice simulation, silicon characterization (DC/AC/RF) and data analysis
5. Extremely detail oriented with strong analytical, communication, and multitasking skills
6. Mix of hands-on and project management skills
Additional Job Description:
Compensation and Benefits
The annual base salary range for this position is $108,000 - $172,800.
As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
