Role SummaryMetaDefender NetWall is OPSWAT's hardware-enforced boundary between networks that must never be able to talk back - a combined hardware and software product deployed across critical infrastructure, defense, and government. This role builds the layer that makes that guarantee physical rather than declared: protocol termination, one-way transport, and content filtering enforced in FPGA (Field-Programmable Gate Array) silicon, at rates no general-purpose processor can sustain.
The Engineering Manager owns the FPGA discipline end to end - silicon and board selection, RTL (Register-Transfer Level) architecture, verification strategy, timing closure, toolchains, IP (Intellectual Property) licensing, the bring-up lab, and the team that does the work - and partners daily with software engineering, product, certification, QA (Quality Assurance), manufacturing, and supply chain. Success in the first twelve months means a working hardware datapath, a verified first protocol running in gateware, and an FPGA team that did not exist before - not the volume of RTL written.
What Comes With the Role - An installed base across energy, manufacturing, defense, government, transportation, and healthcare, already running on the NetWall unidirectional and bilateral security gateways
- An existing Common Criteria EAL4+ certification to extend rather than earn, and certified optical isolation hardware already in the product
- An R&D (Research and Development) organization of approximately 50 engineers, and the MetaDefender® platform - Multiscanning, Deep CDR™ Technology, Proactive DLP™ Technology, and policy enforcement - to build on rather than replicate
- A funded multi-year program to take the line to 100 Gbps and to NCDSMO (National Cross Domain Strategy and Management Office) Raise the Bar
- Budget and hiring authority to build the FPGA team from the first engineer, outside the standard requisition process
Key Responsibilities - Own the FPGA discipline for the NetWall line - RTL architecture, verification strategy, timing closure, coding standards, IP selection, build and regression infrastructure, and the hiring and development of the engineers who do it
- Select the silicon and the boards - evaluate FPGA families and COTS (Commercial Off-The-Shelf) cards against sustained line rate, fabric and transceiver headroom, PCIe (Peripheral Component Interconnect Express) generation, optical cage compatibility, lead time, and licence cost - and own the vendor relationships that follow
- Build the one-way datapath in gateware - framing, link supervision, no back-channel, fail-closed behaviour on every error path, and re-assembly on the receiving side
- Move protocol termination into hardware - TCP (Transmission Control Protocol) state machines, and in time TLS (Transport Layer Security) termination and re-origination - terminating on the sending side and re-originating on the receiving side with no acknowledgement path across the boundary
- Own verification as a first-class deliverable - UVM (Universal Verification Methodology) environments, constrained-random regression, coverage closure, and formal proof of the properties certification depends on: always invoked, non-bypassable, fail-closed
- Deliver the design independence that certification requires - two filter implementations on two silicon lineages, two toolchains, two teams, one shared implementation-neutral specification, and the analysis that demonstrates no common-mode defect can exist
- Own the hardware and software interface with software engineering - PCIe endpoints, DMA (Direct Memory Access) engines, driver contracts, and the boundary decisions that determine what runs in gateware and what runs on the host
- Partner with certification on evidence as the design is built, not afterwards - design documentation, requirement traceability, and the authorship provenance a Common Criteria or NCDSMO assessment will ask for years after the code was written
- Work AI-natively with your team - use modern AI and agentic tools to explore architectures, generate and review testbenches, analyze waveforms and regression output, and accelerate verification, while holding provenance discipline on anything entering the certified boundary
- Own timing, area, power, and cost - close timing on large designs at line rate, and know the device, licence, and board cost your architecture commits the product to
- Own the bring-up lab - boards, optics, traffic generation, protocol analysis, and the test capability the program depends on
- Build and lead the team - recruit senior FPGA engineers in a scarce market, set the technical bar, and grow the discipline from the first hire to two independent implementation teams
Required Qualifications - Five or more years in FPGA development, including production RTL in a shipping product and experience leading or managing FPGA engineers
- Deep SystemVerilog or VHDL, with genuine ownership of architecture, verification, and timing closure on large designs - not module-level contribution
- High-speed interface experience - multi-gigabit transceivers, Ethernet MAC (Media Access Control) and PCS (Physical Coding Sublayer), PCIe endpoints, and DMA
- Demonstrated protocol implementation in hardware - parsing, state machines, or offload - not only datapath or signal processing
- Verification depth: UVM, constrained-random and coverage-driven methodology, and exposure to formal property verification
- Fluent in at least one major toolchain - AMD Vivado or Altera Quartus Prime Pro - and able to stand up build and regression infrastructure from scratch
- Demonstrated AI-native working style, with concrete examples of using AI and agentic tools to design, verify, analyze, and document - an expectation of this role, not a nice-to-have
- Technical depth sufficient to hold meaningful conversations about Linux drivers, networking, security architecture, and system performance on either side of the hardware boundary
- US person - United States citizen or lawful permanent resident - and eligible for a security clearance
- Bias toward action - able to make good decisions without perfect information and keep the team moving
- Professional fluency in English
Nice-to-Have - Cross-domain solutions, data diodes, guards, or other high-assurance security hardware
- Common Criteria, FIPS 140-3, or NCDSMO Raise the Bar experience as a technical contributor or owner
- Active US security clearance
- Formal verification of security properties, or design assurance in avionics, rail, or nuclear instrumentation
- 100 Gbps networking, TCP offload, or TLS acceleration in hardware
- Experience across both AMD and Altera toolchains
- Critical infrastructure, OT (Operational Technology), or industrial environments
