Qualifications

• Master's Degree or equivalent in Electrical/Computer Engineering or Computer Science with 6+ years experience, or Bachelor's Degree with 8+ years experience
• Experience with Verification Test Planning using tools like Cadence ePlanner
• Proficient in EDA Tools such as Cadence Xcelium and Simvision
• Familiar with System Verilog Constraint Random Testing, Assertions and Functional Coverage
• Experience with UVM Testbench component and test sequence development
• Expertise in Verification IP integration
• Knowledge of Industry Standard Protocols like AXI, PCIe, DDR3/4/5

Responsibilities

• Plan and execute FPGA verification projects under the guidance of a Verification Lead
• Interface with hardware, software, and applications teams
• Develop and integrate UVM Testbench components
• Create verification test plans and strategies
• Conduct functional coverage analysis and random testing using System Verilog
• Integrate Verification IP and reference models
• Collaborate with cross-functional teams to resolve verification issues

Benefits

• Comprehensive health insurance including medical, dental, and vision
• Flexible Spending Accounts for healthcare and dependent care
• Retirement savings plans to help secure your future
• Life and disability insurance for added security
• Paid vacation and holidays for work-life balance
• Tuition assistance programs for continuing education
• Employee wellness programs to promote well-being